📄 timecontrol.tan.rpt
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; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_tens[2]~reg0 ; hour[0]~reg0 ; clk ; clk ; None ; None ; 1.829 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; hour[0]~reg0 ; hour[1]~reg0 ; clk ; clk ; None ; None ; 1.768 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[3]~reg0 ; minute_tens[1]~reg0 ; clk ; clk ; None ; None ; 1.738 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[3]~reg0 ; minute_tens[0]~reg0 ; clk ; clk ; None ; None ; 1.733 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[3]~reg0 ; minute_tens[2]~reg0 ; clk ; clk ; None ; None ; 1.731 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_tens[2]~reg0 ; hour[1]~reg0 ; clk ; clk ; None ; None ; 1.626 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_tens[1]~reg0 ; hour[0]~reg0 ; clk ; clk ; None ; None ; 1.537 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[2]~reg0 ; minute_tens[1]~reg0 ; clk ; clk ; None ; None ; 1.531 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[2]~reg0 ; minute_tens[0]~reg0 ; clk ; clk ; None ; None ; 1.526 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[2]~reg0 ; minute_tens[2]~reg0 ; clk ; clk ; None ; None ; 1.524 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_tens[1]~reg0 ; hour[1]~reg0 ; clk ; clk ; None ; None ; 1.489 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[1]~reg0 ; minute_ones[3]~reg0 ; clk ; clk ; None ; None ; 1.349 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_tens[0]~reg0 ; minute_tens[1]~reg0 ; clk ; clk ; None ; None ; 1.344 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_tens[0]~reg0 ; minute_tens[2]~reg0 ; clk ; clk ; None ; None ; 1.343 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_tens[0]~reg0 ; minute_tens[0]~reg0 ; clk ; clk ; None ; None ; 1.343 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_tens[0]~reg0 ; hour[1]~reg0 ; clk ; clk ; None ; None ; 1.343 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[1]~reg0 ; minute_ones[1]~reg0 ; clk ; clk ; None ; None ; 1.343 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[2]~reg0 ; minute_ones[2]~reg0 ; clk ; clk ; None ; None ; 1.313 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[0]~reg0 ; minute_ones[3]~reg0 ; clk ; clk ; None ; None ; 1.210 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[0]~reg0 ; minute_ones[1]~reg0 ; clk ; clk ; None ; None ; 1.206 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[0]~reg0 ; minute_ones[0]~reg0 ; clk ; clk ; None ; None ; 1.206 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_tens[1]~reg0 ; minute_tens[2]~reg0 ; clk ; clk ; None ; None ; 1.205 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_tens[1]~reg0 ; minute_tens[0]~reg0 ; clk ; clk ; None ; None ; 1.203 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_tens[1]~reg0 ; minute_tens[1]~reg0 ; clk ; clk ; None ; None ; 1.194 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; hour[1]~reg0 ; hour[1]~reg0 ; clk ; clk ; None ; None ; 1.126 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[1]~reg0 ; minute_ones[2]~reg0 ; clk ; clk ; None ; None ; 1.091 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[3]~reg0 ; minute_ones[1]~reg0 ; clk ; clk ; None ; None ; 1.089 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[3]~reg0 ; minute_ones[3]~reg0 ; clk ; clk ; None ; None ; 1.082 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_tens[2]~reg0 ; minute_tens[1]~reg0 ; clk ; clk ; None ; None ; 1.061 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_tens[2]~reg0 ; minute_tens[2]~reg0 ; clk ; clk ; None ; None ; 1.059 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_tens[2]~reg0 ; minute_tens[0]~reg0 ; clk ; clk ; None ; None ; 1.059 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; hour[0]~reg0 ; hour[0]~reg0 ; clk ; clk ; None ; None ; 1.014 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[0]~reg0 ; minute_ones[2]~reg0 ; clk ; clk ; None ; None ; 0.931 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[2]~reg0 ; minute_ones[1]~reg0 ; clk ; clk ; None ; None ; 0.890 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; minute_ones[2]~reg0 ; minute_ones[3]~reg0 ; clk ; clk ; None ; None ; 0.882 ns ;
+-------+------------------------------------------------+---------------------+---------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+---------------------+----------------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+---------------------+----------------+------------+
; N/A ; None ; 7.102 ns ; hour[1]~reg0 ; hour[1] ; clk ;
; N/A ; None ; 6.905 ns ; minute_ones[2]~reg0 ; minute_ones[2] ; clk ;
; N/A ; None ; 6.904 ns ; minute_ones[1]~reg0 ; minute_ones[1] ; clk ;
; N/A ; None ; 6.900 ns ; minute_ones[3]~reg0 ; minute_ones[3] ; clk ;
; N/A ; None ; 6.891 ns ; minute_ones[0]~reg0 ; minute_ones[0] ; clk ;
; N/A ; None ; 6.834 ns ; minute_tens[2]~reg0 ; minute_tens[2] ; clk ;
; N/A ; None ; 6.456 ns ; minute_tens[1]~reg0 ; minute_tens[1] ; clk ;
; N/A ; None ; 6.454 ns ; minute_tens[0]~reg0 ; minute_tens[0] ; clk ;
; N/A ; None ; 6.446 ns ; hour[0]~reg0 ; hour[0] ; clk ;
+-------+--------------+------------+---------------------+----------------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
Info: Processing started: Wed Jul 09 22:43:52 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off TimeControl -c TimeControl --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 264.55 MHz between source register "minute_tens[0]~reg0" and destination register "minute_ones[0]~reg0" (period= 3.78 ns)
Info: + Longest register to register delay is 3.519 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y15_N9; Fanout = 7; REG Node = 'minute_tens[0]~reg0'
Info: 2: + IC(1.239 ns) + CELL(0.590 ns) = 1.829 ns; Loc. = LC_X1_Y14_N4; Fanout = 1; COMB Node = 'always0~22'
Info: 3: + IC(1.212 ns) + CELL(0.478 ns) = 3.519 ns; Loc. = LC_X1_Y15_N3; Fanout = 6; REG Node = 'minute_ones[0]~reg0'
Info: Total cell delay = 1.068 ns ( 30.35 % )
Info: Total interconnect delay = 2.451 ns ( 69.65 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.954 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 9; CLK Node = 'clk'
Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y15_N3; Fanout = 6; REG Node = 'minute_ones[0]~reg0'
Info: Total cell delay = 2.180 ns ( 73.80 % )
Info: Total interconnect delay = 0.774 ns ( 26.20 % )
Info: - Longest clock path from clock "clk" to source register is 2.954 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 9; CLK Node = 'clk'
Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y15_N9; Fanout = 7; REG Node = 'minute_tens[0]~reg0'
Info: Total cell delay = 2.180 ns ( 73.80 % )
Info: Total interconnect delay = 0.774 ns ( 26.20 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "hour[1]" through register "hour[1]~reg0" is 7.102 ns
Info: + Longest clock path from clock "clk" to source register is 2.954 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 9; CLK Node = 'clk'
Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y15_N8; Fanout = 3; REG Node = 'hour[1]~reg0'
Info: Total cell delay = 2.180 ns ( 73.80 % )
Info: Total interconnect delay = 0.774 ns ( 26.20 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 3.924 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y15_N8; Fanout = 3; REG Node = 'hour[1]~reg0'
Info: 2: + IC(1.800 ns) + CELL(2.124 ns) = 3.924 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'hour[1]'
Info: Total cell delay = 2.124 ns ( 54.13 % )
Info: Total interconnect delay = 1.800 ns ( 45.87 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 111 megabytes of memory during processing
Info: Processing ended: Wed Jul 09 22:43:55 2008
Info: Elapsed time: 00:00:03
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