timecontrol.sim.rpt

定时控制电路

; |TimeControl|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |TimeControl|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0]      ; cout             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |TimeControl|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; sout             ;
+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                     ;
+-------------------------------------------------------------+-------------------------------------------------------------+------------------+
; Node Name                                                   ; Output Port Name                                            ; Output Port Type ;
+-------------------------------------------------------------+-------------------------------------------------------------+------------------+
; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[0]~0 ; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[0]~0 ; out0             ;
; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[0]   ; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[0]   ; out0             ;
; |TimeControl|lpm_add_sub:Add2|addcore:adder|_~1             ; |TimeControl|lpm_add_sub:Add2|addcore:adder|_~1             ; out0             ;
; |TimeControl|lpm_add_sub:Add2|addcore:adder|_~2             ; |TimeControl|lpm_add_sub:Add2|addcore:adder|_~2             ; out0             ;
; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[1]~1 ; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[1]~1 ; out0             ;
; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[1]   ; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[1]   ; out0             ;
; |TimeControl|lpm_add_sub:Add2|addcore:adder|_~4             ; |TimeControl|lpm_add_sub:Add2|addcore:adder|_~4             ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[0]~0 ; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[0]~0 ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[0]   ; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[0]   ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~1             ; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~1             ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~2             ; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~2             ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[2]~1 ; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[2]~1 ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[2]   ; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[2]   ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[1]   ; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[1]   ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~4             ; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~4             ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~5             ; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~5             ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[0]   ; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[0]   ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~1             ; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~1             ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~2             ; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~2             ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[3]   ; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[3]   ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[2]   ; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[2]   ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[1]   ; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[1]   ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~4             ; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~4             ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~5             ; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~5             ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~6             ; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~6             ; out0             ;
+-------------------------------------------------------------+-------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                                     ;
+-------------------------------------------------------------+-------------------------------------------------------------+------------------+
; Node Name                                                   ; Output Port Name                                            ; Output Port Type ;
+-------------------------------------------------------------+-------------------------------------------------------------+------------------+
; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[0]~0 ; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[0]~0 ; out0             ;
; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[0]   ; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[0]   ; out0             ;
; |TimeControl|lpm_add_sub:Add2|addcore:adder|_~1             ; |TimeControl|lpm_add_sub:Add2|addcore:adder|_~1             ; out0             ;
; |TimeControl|lpm_add_sub:Add2|addcore:adder|_~2             ; |TimeControl|lpm_add_sub:Add2|addcore:adder|_~2             ; out0             ;
; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[1]~1 ; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[1]~1 ; out0             ;
; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[1]   ; |TimeControl|lpm_add_sub:Add2|addcore:adder|datab_node[1]   ; out0             ;
; |TimeControl|lpm_add_sub:Add2|addcore:adder|_~4             ; |TimeControl|lpm_add_sub:Add2|addcore:adder|_~4             ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[0]~0 ; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[0]~0 ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[0]   ; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[0]   ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~1             ; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~1             ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~2             ; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~2             ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[2]~1 ; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[2]~1 ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[2]   ; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[2]   ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[1]   ; |TimeControl|lpm_add_sub:Add1|addcore:adder|datab_node[1]   ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~4             ; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~4             ; out0             ;
; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~5             ; |TimeControl|lpm_add_sub:Add1|addcore:adder|_~5             ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[0]   ; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[0]   ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~1             ; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~1             ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~2             ; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~2             ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[3]   ; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[3]   ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[2]   ; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[2]   ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[1]   ; |TimeControl|lpm_add_sub:Add0|addcore:adder|datab_node[1]   ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~4             ; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~4             ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~5             ; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~5             ; out0             ;
; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~6             ; |TimeControl|lpm_add_sub:Add0|addcore:adder|_~6             ; out0             ;
+-------------------------------------------------------------+-------------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Wed Jul 09 21:36:31 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off TimeControl -c TimeControl
Info: Using vector source file "E:/学习资料/2007-2008学年夏季小学期/电子技术课程设计/FPGA/基础实验/TimeControl/TimeControl.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      79.55 %
Info: Number of transitions in simulation is 5654
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 100 megabytes of memory during processing
    Info: Processing ended: Wed Jul 09 21:36:34 2008
    Info: Elapsed time: 00:00:03