timecontrol.v

定时控制电路

module TimeControl(clk,reset,hour,minute_tens,minute_ones);
	input			clk,reset;
	output[1:0]		hour;
	output[2:0]		minute_tens;
	output[3:0]		minute_ones;
	reg[1:0]		hour;
	reg[2:0]		minute_tens;
	reg[3:0]		minute_ones;
		always@(posedge clk or posedge reset)
			begin
				//Clear
				if(reset)
					begin
						hour <= 0;
						minute_tens <= 0;
						minute_ones <= 0;
					end
				//Count
				else
					begin
						//get the end,hold
						if(hour == 2 && minute_tens == 4 && minute_ones == 8)				
							begin
								hour <= hour;
								minute_ones <= minute_ones;
								minute_tens <= minute_tens;
							end
						//Count
						else
							begin
								minute_ones <= minute_ones + 1;
								if(minute_ones == 9)
									begin
										minute_tens <= minute_tens + 1;
										minute_ones <= 0;
									end
								if(minute_tens == 5)
									begin
										hour <= hour + 1;
										minute_tens <= 0;
									end
							end
					end
			end
endmodule