ad7304.txt

5个模数转换器adc的vhdl源码 5个模数转换器adc的vhdl源码

                    MsgOn          => MsgOn,
                    Violation      => Pviol_CLK
                    );

                VitalPeriodPulseCheck (
                    TestSignal     => CLRNeg,
                    TestSignalName => "CLRNeg",
                    PulseWidthLow  => tpw_CLRNeg_negedge,
                    HeaderMsg      => InstancePath & partID,
                    CheckEnabled   => TRUE,
                    PeriodData     => PD_CLRNeg,
                    XOn            => XOn,
                    MsgOn          => MsgOn,
                    Violation      => Pviol_CLRNeg
                    );

                VitalPeriodPulseCheck (
                    TestSignal      => LDACNeg,
                    TestSignalName  => "LDACNeg",
                    PulseWidthLow   => tpw_LDACNeg_negedge,
                    HeaderMsg       => InstancePath & partID,
                    CheckEnabled    => TRUE,
                    PeriodData      => PD_LDACNeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Pviol_LDACNeg
                    );

                Violation :=
                    Tviol_CSNeg_CLK OR Tviol_SDI_CLK OR Tviol_LDACNeg_CLK
                             OR Pviol_CLK OR Pviol_CLRNeg OR Pviol_LDACNeg;

                ASSERT Violation = '0'
                    REPORT InstancePath & partID & ": simulation may be" &
                    " inaccurate due to timing violations"
                    SEVERITY Warning;
            END IF;

            -------------------------------------------------------------------
            -- Functionality Section
            -------------------------------------------------------------------
            IF rising_edge(CLK_nwv) AND current_state = SERIAL THEN
                shiftData(SDI_nwv);
            END IF;
            IF rising_edge(CSNeg_nwv) AND current_state = SERIAL THEN
                CASE to_nat(Address) IS
                    WHEN 0 =>
                        inregA <= Data;
                    WHEN 1 =>
                        inregB <= Data;
                    WHEN 2 =>
                        inregC <= Data;
                    WHEN 3 =>
                        inregD <= Data;
                    WHEN OTHERS =>
                        NULL;
                END CASE;
                update <= true, false AFTER 1 ns;
            END IF;
            IF CLRNeg_nwv='0' THEN
                inregA <= (OTHERS => '0');
                inregB <= (OTHERS => '0');
                inregC <= (OTHERS => '0');
                inregD <= (OTHERS => '0');
                shift_reg <= (OTHERS => '0');
            END IF;
        END PROCESS digital;

        -- purpose: Convert to analog value
        -- type   : combinational
        -- inputs : decregA
        -- outputs: VOUTA
        DACA : PROCESS (decregA,VrefA_int)
            VARIABLE timeout_A   : time    := tsettle;
            VARIABLE start_value : real    := 0.0;
            -- previous shut down
            VARIABLE prev_SD     : BOOLEAN := true;

        BEGIN  -- PROCESS DACA
            start_value := VOUTA_zd;
            DAConvert(decregA,VrefA_int,EndValA);
            -- this part stores previous mode of operation, shut down or
            -- normal,and calculate time needed for settling of output.
            IF prev_SD THEN
                IF PowerDown OR PowerDownA THEN
                    prev_SD := true;
                ELSE
                    prev_SD := false;
                    timeout_A := tsdr;
                END IF;
            ELSE
                IF PowerDown OR PowerDownA THEN
                    prev_SD := true;
                    timeout_A := tsdn;
                ELSE
                    timeout_A := tsettle;
                END IF;
            END IF;
            StepA :=
                (EndValA - start_value) / real((timeout_A)/100 ns);
            settleA <= '1', '0' AFTER timeout_A;
        END PROCESS DACA;

        out_A: PROCESS (update_outA, settleA) IS
        BEGIN  -- PROCESS out_A
            IF settleA = '0' THEN
                VOUTA_zd <= EndValA;
            ELSE
                update_outA <= NOT update_outA AFTER 100 ns;
                IF update_outA'event THEN
                    VOUTA_zd <= VOUTA_zd + StepA;
                END IF;
            END IF;
        END PROCESS out_A;

        DACB : PROCESS (decregB,VrefB_int)
            VARIABLE timeout_B   : time    := tsettle;
            VARIABLE start_value : real    := 0.0;
            -- previous shut down
            VARIABLE prev_SD     : BOOLEAN := true;

        BEGIN  -- PROCESS DACB
            start_value := VOUTB_zd;
            DAConvert(decregB,VrefB_int,EndValB);
            -- this part stores previous mode of operation, shut down or
            -- normal,and calculate time needed for settling of output.
            IF prev_SD THEN
                IF PowerDown OR PowerDownB THEN
                    prev_SD := true;
                ELSE
                    prev_SD := false;
                    timeout_B := tsdr;
                END IF;
            ELSE
                IF PowerDown OR PowerDownB THEN
                    prev_SD := true;
                    timeout_B := tsdn;
                ELSE
                    timeout_B := tsettle;
                END IF;
            END IF;
            StepB :=
                (EndValB - start_value) / real((timeout_B)/100 ns);
            settleB <= '1', '0' AFTER timeout_B;
        END PROCESS DACB;

        out_B: PROCESS (update_outB, settleB) IS
        BEGIN  -- PROCESS out_B
            IF settleB = '0' THEN
                VOUTB_zd <= EndValB;
            ELSE
                update_outB <= (NOT update_outB) AFTER 100 ns;
                IF update_outB'event THEN
                    VOUTB_zd <= VOUTB_zd + StepB;
                END IF;
            END IF;
        END PROCESS out_B;

        DACC : PROCESS (decregC,VrefC_int)
            VARIABLE timeout_C   : time    := tsettle;
            VARIABLE start_value : real    := 0.0;
            -- previous shut down
            VARIABLE prev_SD     : BOOLEAN := true;

        BEGIN  -- PROCESS DACC
            start_value := VOUTC_zd;
            DAConvert(decregC,VrefC_int,EndValC);
            -- this part stores previous mode of operation, shut down or
            -- normal,and calculate time needed for settling of output.
            IF prev_SD THEN
                IF PowerDown OR PowerDownC THEN
                    prev_SD := true;
                ELSE
                    prev_SD := false;
                    timeout_C := tsdr;
                END IF;
            ELSE
                IF PowerDown OR PowerDownC THEN
                    prev_SD := true;
                    timeout_C := tsdn;
                ELSE
                    timeout_C := tsettle;
                END IF;
            END IF;
            StepC :=
                (EndValC - start_value) / real((timeout_C)/100 ns);
            settleC <= '1', '0' AFTER timeout_C;
        END PROCESS DACC;

        out_C: PROCESS (update_outC, settleC) IS
        BEGIN  -- PROCESS out_C
            IF settleC = '0' THEN
                VOUTC_zd <= EndValC;
            ELSE
                update_outC <= (NOT update_outC) AFTER 100 ns;
                IF update_outC'event THEN
                    VOUTC_zd <= VOUTC_zd + StepC;
                END IF;
            END IF;
        END PROCESS out_C;

        DACD : PROCESS (decregD,VrefD_int)
            VARIABLE timeout_D   : time    := tsettle;
            VARIABLE start_value : real    := 0.0;
            -- previous shut down
            VARIABLE prev_SD     : BOOLEAN := true;

        BEGIN  -- PROCESS DACD
            start_value := VOUTD_zd;
            DAConvert(decregD,VrefD_int,EndValD);
            -- this part stores previous mode of operation, shut down or
            -- normal,and calculate time needed for settling of output.
            IF prev_SD THEN
                IF PowerDown OR PowerDownD THEN
                    prev_SD := true;
                ELSE
                    prev_SD := false;
                    timeout_D := tsdr;
                END IF;
            ELSE
                IF PowerDown OR PowerDownD THEN
                    prev_SD := true;
                    timeout_D := tsdn;
                ELSE
                    timeout_D := tsettle;
                END IF;
            END IF;
            StepD :=
                (EndValD - start_value) / real((timeout_D)/100 ns);
            settleD <= '1', '0' AFTER timeout_D;
        END PROCESS DACD;

        out_D: PROCESS (update_outD, settleD) IS
        BEGIN  -- PROCESS out_D
            IF settleD = '0' THEN
                VOUTD_zd <= EndValD;
            ELSE
                update_outD <= (NOT update_outD) AFTER 100 ns;
                IF update_outD'event THEN
                    VOUTD_zd <= VOUTD_zd + StepD;
                END IF;
            END IF;
        END PROCESS out_D;

        VOUTA <= VOUTA_zd;
        VOUTB <= VOUTB_zd;
        VOUTC <= VOUTC_zd;
        VOUTD <= VOUTD_zd;

    END BLOCK;
END vhdl_behavioral;