ad7395.vhd

5个模数转换器adc的vhdl源码 5个模数转换器adc的vhdl源码

--------------------------------------------------------------------------------
-- File Name: ad7395.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 2003 Free Model Foundry; http://www.FreeModelFoundry.com
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: | author:   | mod date: | changes made:
--  V1.0    M.Radmanovic  03 Jul 25   Initial release
--
-- This model must be compiled without VITAL compliance checking
--------------------------------------------------------------------------------
-- PART DESCRIPTION:
--
-- Library:    CONVERTER_VHDL
-- Technology: CMOS
-- Part:       AD7395
-- Description: Dual, Serial Input 10-Bit DAC
--
-- Known deficiencies: When SHDNNeg = '0' analog outputs should (but do not)
-- go high impedance.
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY ad7395 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_SDI                    : VitalDelayType01 := VitalZeroDelay01;
        tipd_LDANeg                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_LDBNeg                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLK                    : VitalDelayType01 := VitalZeroDelay01;
        tipd_CSNeg                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_RSNeg                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_MSB                    : VitalDelayType01 := VitalZeroDelay01;
        tipd_SHDNNeg                : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        -- tsetup values: setup times
        tsetup_SDI_CLK              : VitalDelayType := UnitDelay;
        tsetup_LDANeg_CLK           : VitalDelayType := UnitDelay;
        -- thold values: hold times
        thold_SDI_CLK               : VitalDelayType := UnitDelay;
        thold_LDANeg_CLK            : VitalDelayType := UnitDelay;
        -- tpw values: pulse widths
        tpw_CLK_posedge             : VitalDelayType := UnitDelay;
        tpw_CLK_negedge             : VitalDelayType := UnitDelay;
        tpw_LDANeg_negedge          : VitalDelayType := UnitDelay;
        tpw_RSNeg_negedge           : VitalDelayType := UnitDelay;
         -- analog generics: value of Vref input In Volts
        Vref                : real := 2.5;
        -- generic control parameters
        InstancePath        : STRING  := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN := DefaultTimingChecks;
        MsgOn               : BOOLEAN := DefaultMsgOn;
        XOn                 : BOOLEAN := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING  := DefaultTimingModel
    );
    PORT (
        SDI             : IN    std_ulogic := 'U';
        LDANeg          : IN    std_ulogic := 'U';
        LDBNeg          : IN    std_ulogic := 'U';
        OUTA            : OUT   real := 0.0;
        OUTB            : OUT   real := 0.0;
        CLK             : IN    std_ulogic := 'U';
        CSNeg           : IN    std_ulogic := 'U';
        RSNeg           : IN    std_ulogic := 'U';
        MSB             : IN    std_ulogic := 'U';
        SHDNNeg         : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of ad7395 : ENTITY IS TRUE;
END ad7395;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of ad7395 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID             : STRING  := "ad7395";
    CONSTANT resolution         : INTEGER := 10;

    SUBTYPE dacval_type IS   NATURAL RANGE 0 TO (2**resolution-1);

    SIGNAL SDI_ipd              : std_ulogic := 'U';
    SIGNAL LDANeg_ipd           : std_ulogic := 'U';
    SIGNAL LDBNeg_ipd           : std_ulogic := 'U';
    SIGNAL CLK_ipd              : std_ulogic := 'U';
    SIGNAL CSNeg_ipd            : std_ulogic := 'U';
    SIGNAL RSNeg_ipd            : std_ulogic := 'U';
    SIGNAL MSB_ipd              : std_ulogic := 'U';
    SIGNAL SHDNNeg_ipd          : std_ulogic := 'U';
    SIGNAL UPDATEA              : std_ulogic := '0';
    SIGNAL UPDATEB              : std_ulogic := '0';
    SIGNAL dacvalA              : dacval_type;
    SIGNAL dacvalB              : dacval_type;

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1  : VitalWireDelay (SDI_ipd, SDI, tipd_SDI);
        w_2  : VitalWireDelay (LDANeg_ipd, LDANeg, tipd_LDANeg);
        w_3  : VitalWireDelay (LDBNeg_ipd, LDBNeg, tipd_LDBNeg);
        w_6  : VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        w_7  : VitalWireDelay (CSNeg_ipd, CSNeg, tipd_CSNeg);
        w_8  : VitalWireDelay (RSNeg_ipd, RSNeg, tipd_RSNeg);
        w_9  : VitalWireDelay (MSB_ipd, MSB, tipd_MSB);
        w_10 : VitalWireDelay (SHDNNeg_ipd, SHDNNeg, tipd_SHDNNeg);

    END BLOCK;

    Behavior : BLOCK

        SIGNAL OUTA_zd              : real := 0.0;
        SIGNAL OUTB_zd              : real := 0.0;

    BEGIN
    ----------------------------------------------------------------------------
     -- Behavior Process
    ----------------------------------------------------------------------------
    digital : PROCESS (SDI_ipd, CLK_ipd, LDANeg_ipd, LDBNeg_ipd,
                       CSNeg_ipd, RSNeg_ipd, MSB_ipd, SHDNNeg_ipd)

    -- Timing Check Variables
    VARIABLE Tviol_SDI_CLK      : X01 := '0';
    VARIABLE TD_SDI_CLK         : VitalTimingDataType;

    VARIABLE Tviol_LDANeg_CLK   : X01 := '0';
    VARIABLE TD_LDANeg_CLK      : VitalTimingDataType;

    VARIABLE Tviol_LDBNeg_CLK   : X01 := '0';
    VARIABLE TD_LDBNeg_CLK      : VitalTimingDataType;

    VARIABLE PD_CLK             : VitalPeriodDataType := VitalPeriodDataInit;
    VARIABLE Pviol_CLK          : X01 := '0';

    VARIABLE PD_LDANeg          : VitalPeriodDataType := VitalPeriodDataInit;
    VARIABLE Pviol_LDANeg       : X01 := '0';

    VARIABLE PD_LDBNeg          : VitalPeriodDataType := VitalPeriodDataInit;
    VARIABLE Pviol_LDBNeg       : X01 := '0';

    VARIABLE PD_RSNeg           : VitalPeriodDataType := VitalPeriodDataInit;
    VARIABLE Pviol_RSNeg        : X01 := '0';

    VARIABLE Violation          : X01 := '0';

    SUBTYPE dacreg_type IS   std_logic_vector(resolution-1 DOWNTO 0);

    VARIABLE inreg              : std_logic_vector(resolution-1 DOWNTO 0);
    VARIABLE dacregA            : dacreg_type;
    VARIABLE dacregB            : dacreg_type;
    VARIABLE LDANeg_nwv         : X01;
    VARIABLE LDBNeg_nwv         : X01;
    VARIABLE CSNeg_nwv          : X01;
    VARIABLE RSNeg_nwv          : X01;
    VARIABLE MSB_nwv            : X01;
    VARIABLE CLK_nwv            : X01;
    VARIABLE SDI_nwv            : X01;
    VARIABLE SHDNNeg_nwv        : X01;

    -- Output Glitch Detection Variables

    BEGIN

        SDI_nwv     := to_X01(SDI_ipd);
        LDANeg_nwv  := to_X01(LDANeg_ipd);
        LDBNeg_nwv  := to_X01(LDBNeg_ipd);
        CLK_nwv     := to_X01(CLK_ipd);
        CSNeg_nwv   := to_X01(CSNeg_ipd);
        RSNeg_nwv   := to_X01(RSNeg_ipd);
        MSB_nwv     := to_X01(MSB_ipd);
        SHDNNeg_nwv := to_X01(SHDNNeg_ipd);

        ------------------------------------------------------------------------
        -- Timing Check Section
        ------------------------------------------------------------------------
        IF (TimingChecksOn) THEN

            VitalSetupHoldCheck (
                TestSignal      => SDI_ipd,
                TestSignalName  => "SDI",
                RefSignal       => CLK_ipd,
                RefSignalName   => "CLK",
                SetupHigh       => tsetup_SDI_CLK,
                SetupLow        => tsetup_SDI_CLK,
                HoldHigh        => thold_SDI_CLK,
                HoldLow         => thold_SDI_CLK,
                CheckEnabled    => (RSNeg_nwv = '1' AND CSNeg_nwv = '0'),
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_SDI_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_SDI_CLK
            );

            VitalSetupHoldCheck (
                TestSignal      => LDANeg_ipd,
                TestSignalName  => "LDANeg",
                RefSignal       => CLK_ipd,
                RefSignalName   => "CLK",
                SetupHigh       => tsetup_LDANeg_CLK,
                SetupLow        => tsetup_LDANeg_CLK,
                HoldHigh        => thold_LDANeg_CLK,
                HoldLow         => thold_LDANeg_CLK,
                CheckEnabled    => (RSNeg_nwv = '1' AND CSNeg_nwv = '0'),
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_LDANeg_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_LDANeg_CLK
            );

            VitalSetupHoldCheck (
                TestSignal      => LDBNeg_ipd,
                TestSignalName  => "LDBNeg",
                RefSignal       => CLK_ipd,
                RefSignalName   => "CLK",
                SetupHigh       => tsetup_LDANeg_CLK,
                SetupLow        => tsetup_LDANeg_CLK,
                HoldHigh        => thold_LDANeg_CLK,
                HoldLow         => thold_LDANeg_CLK,
                CheckEnabled    => (RSNeg_nwv = '1' AND CSNeg_nwv = '0'),
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_LDBNeg_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_LDBNeg_CLK
            );

            VitalPeriodPulseCheck (
                TestSignal      => CLK_ipd,
                TestSignalName  => "CLK_ipd",
                PulseWidthHigh  => tpw_CLK_posedge,
                PulseWidthLow   => tpw_CLK_negedge,
                HeaderMsg       => InstancePath & partID,
                CheckEnabled    => (RSNeg_nwv = '1' AND CSNeg_nwv = '0'),
                PeriodData      => PD_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_CLK
            );

            VitalPeriodPulseCheck (
                TestSignal      => LDANeg_ipd,
                TestSignalName  => "LDANeg",
                PulseWidthLow   => tpw_LDANeg_negedge,
                HeaderMsg       => InstancePath & partID,
                CheckEnabled    => (RSNeg_nwv = '1'),
                PeriodData      => PD_LDANeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_LDANeg
            );

            VitalPeriodPulseCheck (
                TestSignal      => LDBNeg_ipd,
                TestSignalName  => "LDBNeg",
                PulseWidthLow   => tpw_LDANeg_negedge,
                HeaderMsg       => InstancePath & partID,
                CheckEnabled    => (RSNeg_nwv = '1'),
                PeriodData      => PD_LDBNeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_LDBNeg
            );

            VitalPeriodPulseCheck (
                TestSignal      => RSNeg_ipd,
                TestSignalName  => "RSNeg",
                PulseWidthLow   => tpw_RSNeg_negedge,
                HeaderMsg       => InstancePath & partID,
                CheckEnabled    => TRUE,
                PeriodData      => PD_RSNeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_RSNeg
            );

            Violation := Tviol_SDI_CLK OR Tviol_LDANeg_CLK OR
                         Tviol_LDBNeg_CLK OR Pviol_CLK OR Pviol_LDANeg OR
                         Pviol_LDBNeg OR Pviol_RSNeg;
            ASSERT Violation = '0'
                REPORT InstancePath & partID & ": simulation may be" &
                       " inaccurate due to timing violations"
                SEVERITY Warning;

        END IF;
        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------

        IF RSNeg_nwv = '0' THEN    -- reset
            IF MSB_nwv = '1' THEN
                dacregA := "1000000000";
                dacregB := "1000000000";
            ELSE
                dacregA := (others => '0');
                dacregB := (others => '0');
            END IF;
            dacvalA <= to_nat(dacregA);
            dacvalB <= to_nat(dacregB);
        ELSIF CSNeg_nwv = '0' AND RSNeg_nwv = '1' THEN
            IF rising_edge(CLK_ipd) THEN
                FOR I IN resolution-1 DOWNTO 1 LOOP
                    inreg(i) := inreg(i-1);
                END LOOP;
                inreg(0) := SDI_nwv;
                IF LDANeg_nwv = '0' OR LDBNeg_nwv = '0' THEN
                    ASSERT false
                    REPORT InstancePath & partID & ": do not clock in" &
                        " while LDANeg or LDBNeg are logic LOW"
                        SEVERITY Warning;
                END IF;
            END IF;
        END IF;
        IF RSNeg_nwv = '1' THEN
            IF LDANeg_nwv = '0' THEN -- load DacA
                dacregA := inreg;
                dacvalA <= to_nat(dacregA);
            END IF;
            IF LDBNeg_nwv = '0' THEN -- load DacB
                dacregB := inreg;
                dacvalB <= to_nat(dacregB);
            END IF;
        END IF;

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
    END PROCESS digital;

    dacA : PROCESS (dacvalA)

    BEGIN

        OUTA_zd <= (REAL(dacvalA) * Vref/REAL(2**resolution));

    END PROCESS dacA;

    dacB : PROCESS (dacvalB)

    BEGIN

        OUTB_zd <= (REAL(dacvalB) * Vref/REAL(2**resolution));

    END PROCESS dacB;

    OUTA <= OUTA_zd WHEN to_X01(SHDNNeg_ipd) = '1' ELSE 0.0;
    OUTB <= OUTB_zd WHEN to_X01(SHDNNeg_ipd) = '1' ELSE 0.0;

    END BLOCK;


END vhdl_behavioral;