ads1286.vhd

5个模数转换器adc的vhdl源码 5个模数转换器adc的vhdl源码

--------------------------------------------------------------------------------
--  File Name: ads1286.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2003 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    03 Jan 10   Initial release
-- 
--  Must be compiled with VITAL compliance checking off
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    CONVERTERS_VHDL
--  Technology: MIXED
--  Part:       ADS1286
-- 
--  Description: Sampling 12-Bit A/D Converter
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY ads1286 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_CLK                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CSNeg               : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_CLK_DOUT             : VitalDelayType01Z := UnitDelay01Z;
        tpd_CSNeg_DOUT           : VitalDelayType01Z := UnitDelay01Z;
        -- tsetup values: setup times
        tsetup_CSNeg_CLK         : VitalDelayType := UnitDelay;
        -- tpw values: pulse widths
        tpw_CLK_posedge          : VitalDelayType := UnitDelay;
        tpw_CLK_negedge          : VitalDelayType := UnitDelay;
        tpw_CSNeg_posedge        : VitalDelayType := UnitDelay;
        tpw_CSNeg_negedge        : VitalDelayType := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_CLK_posedge : VitalDelayType := UnitDelay;
        -- analog generics
        -- value of Vref input In Volts
        Vref                : real    := 5.00;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        CLK             : IN    std_ulogic := 'U';
        DOUT            : OUT   std_ulogic := 'U';
        INP             : IN    real := 0.0;
        INN             : IN    real := 0.0;
        CSNeg           : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of ads1286 : ENTITY IS TRUE;
END ads1286;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of ads1286 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID            : STRING := "ads1286";

    SIGNAL CLK_ipd             : std_ulogic := 'U';
    SIGNAL CSNeg_ipd           : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        w_2 : VitalWireDelay (CSNeg_ipd, CSNeg, tipd_CSNeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Behavior Process
    ----------------------------------------------------------------------------
    convert : PROCESS (CSNeg_ipd, CLK_ipd)

        -- Timing Check Variables
        VARIABLE Tviol_CSNeg_CLK  : X01 := '0';
        VARIABLE TD_CSNeg_CLK     : VitalTimingDataType;

        VARIABLE PD_CLK          : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE Pviol_CLK       : X01 := '0';

        VARIABLE PD_CSNeg        : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE Pviol_CSNeg     : X01 := '0';

        VARIABLE Violation      : X01 := '0';

        TYPE cntdir_type IS (up, down, stop);

        CONSTANT res      : natural := 12; -- resolution in bits
        VARIABLE bitcnt   : natural := 13; -- data bit cntr
        VARIABLE reg    : std_logic_vector(res + 1 DOWNTO 0) := (others => '0');
        VARIABLE D_zd     : std_ulogic := 'Z';
        VARIABLE sample   : real;
        VARIABLE tmpref   : real;
        VARIABLE pwrdn    : boolean := true;
        VARIABLE reset    : boolean := false;
        VARIABLE convert  : boolean := false;
        VARIABLE cntdir   : cntdir_type;

        -- Output Glitch Detection Variables
        VARIABLE D_GlitchData  : VitalGlitchDataType;

    BEGIN
        ------------------------------------------------------------------------
        -- Timing Check Section
        ------------------------------------------------------------------------
        IF (TimingChecksOn) THEN
            VitalSetupHoldCheck (
                TestSignal      => CSNeg_ipd,
                TestSignalName  => "CSNeg",
                RefSignal       => CLK_ipd,
                RefSignalName   => "CLK",
                SetupLow        => tsetup_CSNeg_CLK,
                CheckEnabled    => TRUE,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_CSNeg_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_CSNeg_CLK
            );

            VitalPeriodPulseCheck (
                TestSignal      => CLK_ipd,
                TestSignalName  => "CLK",
                Period          => tperiod_CLK_posedge,
                PulseWidthHigh  => tpw_CLK_posedge,
                PulseWidthLow   => tpw_CLK_negedge,
                HeaderMsg       => InstancePath & partID,
                CheckEnabled    => TRUE,
                PeriodData      => PD_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_CLK
            );

            VitalPeriodPulseCheck (
                TestSignal      => CSNeg_ipd,
                TestSignalName  => "CSNeg",
                PulseWidthHigh  => tpw_CSNeg_posedge,
                PulseWidthLow   => tpw_CSNeg_negedge,
                HeaderMsg       => InstancePath & partID,
                CheckEnabled    => TRUE,
                PeriodData      => PD_CSNeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_CSNeg
            );

            Violation := Tviol_CSNeg_CLK OR Pviol_CLK OR Pviol_CSNeg;

        END IF;

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        IF falling_edge(CSNeg_ipd) THEN   -- sample input
            reset := true;
            sample := INP - INN;
        ELSIF rising_edge(CSNeg_ipd) THEN   -- power down
            D_zd := 'Z';
            pwrdn := true;
            bitcnt :=  res + 1;
        END IF;

        IF to_UX01(CSNeg_ipd) = '0' THEN
            IF rising_edge(CLK_ipd) THEN
                IF pwrdn AND bitcnt = res + 1 THEN     -- begin
                    convert := true;
                    reset := false;
                    pwrdn := false;
                    cntdir := down;
                END IF;
            ELSIF falling_edge(CLK_ipd) THEN
                IF not pwrdn THEN
                    IF bitcnt > 12 THEN
                        D_zd := 'Z';
                    ELSE
                        D_zd := reg(bitcnt);    -- output data
                    END IF;
                    IF cntdir = down AND not convert THEN
                        bitcnt := bitcnt - 1;
                        IF bitcnt = 0 THEN
                            cntdir := up;
                        END IF;
                    ELSIF cntdir = up THEN
                        bitcnt := bitcnt + 1;
                        IF bitcnt = res THEN
                            cntdir := stop;
                        END IF;
                    END IF;
                END IF;
            END IF;
        END IF;

        IF convert THEN
            tmpref := Vref/2.0;
            FOR b IN (res - 1) DOWNTO 0 LOOP
                IF sample >= tmpref THEN
                    reg(b) := '1';
                    tmpref := tmpref + tmpref/2.0;
                ELSE
                    reg(b) := '0';
                    tmpref := tmpref/2.0;
                END IF;
            END LOOP;
            convert := false;
        END IF;

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01Z (
            OutSignal       => DOUT,
            OutSignalName   => "DOUT",
            OutTemp         => D_zd,
            GlitchData      => D_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => CLK_ipd'LAST_EVENT,
                      PathDelay         => tpd_CLK_DOUT,
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => CSNeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_CSNeg_DOUT,
                      PathCondition     => TRUE)
            )
        );

    END PROCESS convert;
END vhdl_behavioral;