ad7305.txt

5个模数转换器adc的vhdl源码 5个模数转换器adc的vhdl源码

            VARIABLE Tviol_DB_WRNeg         : X01 := '0';
            VARIABLE TD_DB_WRNeg            : VitalTimingDataType;

            VARIABLE Tviol_LDACNeg_WRNeg    : X01 := '0';
            VARIABLE TD_LDACNeg_WRNeg       : VitalTimingDataType;

            VARIABLE PD_LDACNeg             : VitalPeriodDataType :=
                VitalPeriodDataInit;
            VARIABLE Pviol_LDACNeg          : X01 := '0';

            VARIABLE PD_WRNeg               : VitalPeriodDataType :=
                VitalPeriodDataInit;
            VARIABLE Pviol_WRNeg            : X01                 := '0';

            VARIABLE Violation              : X01   := '0';

            VARIABLE inregA                 : stdl8 := (OTHERS => '0');
            VARIABLE inregB                 : stdl8 := (OTHERS => '0');
            VARIABLE inregC                 : stdl8 := (OTHERS => '0');
            VARIABLE inregD                 : stdl8 := (OTHERS => '0');

        BEGIN
            -------------------------------------------------------------------
            -- Timing Check Section
            -------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => A,
                    TestSignalName  => "A",
                    RefSignal       => WRNeg,
                    RefSignalName   => "WRNeg",
                    SetupLow        => tsetup_A0_WRNeg,
                    SetupHigh       => tsetup_A0_WRNeg,
                    HoldLow         => thold_A0_WRNeg,
                    HoldHigh        => thold_A0_WRNeg,
                    CheckEnabled    => true,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & partID,
                    TimingData      => TD_A_WRNeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_A_WRNeg
                    );

                VitalSetupHoldCheck (
                    TestSignal      => DB,
                    TestSignalName  => "DB",
                    RefSignal       => WRNeg,
                    RefSignalName   => "WRNeg",
                    SetupHigh       => tsetup_DB0_WRNeg,
                    SetupLow        => tsetup_DB0_WRNeg,
                    HoldHigh        => thold_DB0_WRNeg,
                    HoldLow         => thold_DB0_WRNeg,
                    CheckEnabled    => true,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & partID,
                    TimingData      => TD_DB_WRNeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_DB_WRNeg
                    );

                VitalSetupHoldCheck (
                    TestSignal     => LDACNeg,
                    TestSignalName => "LDACNeg",
                    RefSignal      => WRNeg,
                    RefSignalName  => "WRNeg",
                    SetupLow       => tsetup_LDACNeg_WRNeg,
                    HoldLow        => thold_LDACNeg_WRNeg,
                    CheckEnabled   => true,
                    RefTransition  => '/',
                    HeaderMsg      => InstancePath & partID,
                    TimingData     => TD_LDACNeg_WRNeg,
                    XOn            => XOn,
                    MsgOn          => MsgOn,
                    Violation      => Tviol_LDACNeg_WRNeg
                    );

                VitalPeriodPulseCheck (
                    TestSignal     => WRNeg,
                    TestSignalName => "WRNeg",
                    PulseWidthLow  => tpw_WRNeg_negedge,
                    HeaderMsg      => InstancePath & partID,
                    CheckEnabled   => TRUE,
                    PeriodData     => PD_WRNeg,
                    XOn            => XOn,
                    MsgOn          => MsgOn,
                    Violation      => Pviol_WRNeg
                    );

                VitalPeriodPulseCheck (
                    TestSignal      => LDACNeg,
                    TestSignalName  => "LDACNeg",
                    PulseWidthLow   => tpw_LDACNeg_negedge,
                    HeaderMsg       => InstancePath & partID,
                    CheckEnabled    => TRUE,
                    PeriodData      => PD_LDACNeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Pviol_LDACNeg
                    );

                Violation :=
                    Tviol_DB_WRNeg OR Tviol_A_WRNeg OR Tviol_LDACNeg_WRNeg
                    OR Pviol_WRNeg OR Pviol_LDACNeg;

                ASSERT Violation = '0'
                    REPORT InstancePath & partID & ": simulation may be" &
                    " inaccurate due to timing violations"
                    SEVERITY Warning;
            END IF;

            -------------------------------------------------------------------
            -- Functionality Section
            -------------------------------------------------------------------
            IF WRNeg = '0' THEN
                CASE to_nat(A) IS
                    WHEN 0 =>
                        inregA := DB;
                    WHEN 1 =>
                        inregB := DB;
                    WHEN 2 =>
                        inregC := DB;
                    WHEN 3 =>
                        inregD := DB;
                    WHEN OTHERS => NULL;
                END CASE;
            END IF;
            IF LDACNeg = '0' THEN
                decregD <= inregD;
                decregC <= inregC;
                decregB <= inregB;
                decregA <= inregA;
            END IF;
        END PROCESS digital;

        -- purpose: Convert to analog value
        -- type   : combinational
        -- inputs : decregA
        -- outputs: VOUTA
        DACA : PROCESS (decregA,Vref_int)
            VARIABLE timeout_A   : time    := tsettle;
            VARIABLE start_value : real    := 0.0;
            -- previous shut down
            VARIABLE prev_SD     : BOOLEAN := true;

        BEGIN  -- PROCESS DACA
            start_value := VOUTA_zd;
            DAConvert(decregA,Vref_int,EndValA);
            -- this part stores previous mode of operation, shut down or
            -- normal,and calculate time needed for settling of output.
            IF prev_SD THEN
                prev_SD := false;
                timeout_A := tsdr;
            ELSE
                timeout_A := tsettle;
            END IF;
            StepA :=
                (EndValA - start_value) / real((timeout_A)/100 ns);
            settleA <= '1', '0' AFTER timeout_A;
        END PROCESS DACA;

        out_A: PROCESS (update_outA, settleA) IS
        BEGIN  -- PROCESS out_A
            IF settleA = '0' THEN
                VOUTA_zd <= EndValA;
            ELSE
                update_outA <= NOT update_outA AFTER 100 ns;
                IF update_outA'event THEN
                    VOUTA_zd <= VOUTA_zd + StepA;
                END IF;
            END IF;
        END PROCESS out_A;

        DACB : PROCESS (decregB,Vref_int)
            VARIABLE timeout_B   : time    := tsettle;
            VARIABLE start_value : real    := 0.0;
            -- previous shut down
            VARIABLE prev_SD     : BOOLEAN := true;

        BEGIN  -- PROCESS DACB
            start_value := VOUTB_zd;
            DAConvert(decregB,Vref_int,EndValB);
            -- this part stores previous mode of operation, shut down or
            -- normal,and calculate time needed for settling of output.
            IF prev_SD THEN
                prev_SD := false;
                timeout_B := tsdr;
            ELSE
                timeout_B := tsettle;
            END IF;
            StepB :=
                (EndValB - start_value) / real((timeout_B)/100 ns);
            settleB <= '1', '0' AFTER timeout_B;
        END PROCESS DACB;

        out_B: PROCESS (update_outB, settleB) IS
        BEGIN  -- PROCESS out_B
            IF settleB = '0' THEN
                VOUTB_zd <= EndValB;
            ELSE
                update_outB <= (NOT update_outB) AFTER 100 ns;
                IF update_outB'event THEN
                    VOUTB_zd <= VOUTB_zd + StepB;
                END IF;
            END IF;
        END PROCESS out_B;

        DACC : PROCESS (decregC,Vref_int)
            VARIABLE timeout_C   : time    := tsettle;
            VARIABLE start_value : real    := 0.0;
            -- previous shut down
            VARIABLE prev_SD     : BOOLEAN := true;

        BEGIN  -- PROCESS DACC
            start_value := VOUTC_zd;
            DAConvert(decregC,Vref_int,EndValC);
            -- this part stores previous mode of operation, shut down or
            -- normal,and calculate time needed for settling of output.
            IF prev_SD THEN
                prev_SD := false;
                timeout_C := tsdr;
            ELSE
                timeout_C := tsettle;
            END IF;
            StepC :=
                (EndValC - start_value) / real((timeout_C)/100 ns);
            settleC <= '1', '0' AFTER timeout_C;
        END PROCESS DACC;

        out_C: PROCESS (update_outC, settleC) IS
        BEGIN  -- PROCESS out_C
            IF settleC = '0' THEN
                VOUTC_zd <= EndValC;
            ELSE
                update_outC <= (NOT update_outC) AFTER 100 ns;
                IF update_outC'event THEN
                    VOUTC_zd <= VOUTC_zd + StepC;
                END IF;
            END IF;
        END PROCESS out_C;

        DACD : PROCESS (decregD,Vref_int)
            VARIABLE timeout_D   : time    := tsettle;
            VARIABLE start_value : real    := 0.0;
            -- previous shut down
            VARIABLE prev_SD     : BOOLEAN := true;

        BEGIN  -- PROCESS DACD
            start_value := VOUTD_zd;
            DAConvert(decregD,Vref_int,EndValD);
            -- this part stores previous mode of operation, shut down or
            -- normal,and calculate time needed for settling of output.
            IF prev_SD THEN
                prev_SD := false;
                timeout_D := tsdr;
            ELSE
                timeout_D := tsettle;
            END IF;
            StepD :=
                (EndValD - start_value) / real((timeout_D)/100 ns);
            settleD <= '1', '0' AFTER timeout_D;
        END PROCESS DACD;

        out_D: PROCESS (update_outD, settleD) IS
        BEGIN  -- PROCESS out_D
            IF settleD = '0' THEN
                VOUTD_zd <= EndValD;
            ELSE
                update_outD <= (NOT update_outD) AFTER 100 ns;
                IF update_outD'event THEN
                    VOUTD_zd <= VOUTD_zd + StepD;
                END IF;
            END IF;
        END PROCESS out_D;

        VOUTA <= VOUTA_zd;
        VOUTB <= VOUTB_zd;
        VOUTC <= VOUTC_zd;
        VOUTD <= VOUTD_zd;

    END BLOCK;
END vhdl_behavioral;