fsm_mealy.map.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 26 21:56:01 2006 " "Info: Processing started: Mon Jun 26 21:56:01 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FSM_Mealy -c FSM_Mealy " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FSM_Mealy -c FSM_Mealy" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FSM_Mealy.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file FSM_Mealy.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FSM_Mealy-behav " "Info: Found design unit 1: FSM_Mealy-behav" {  } { { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 FSM_Mealy " "Info: Found entity 1: FSM_Mealy" {  } { { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "FSM_Mealy " "Info: Elaborating entity \"FSM_Mealy\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk FSM_Mealy.vhd(17) " "Warning: VHDL Process Statement warning at FSM_Mealy.vhd(17): signal \"clk\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 17 0 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|FSM_Mealy\|state 8 0 " "Info: State machine \"\|FSM_Mealy\|state\" contains 8 states and 0 state bits" {  } { { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 12 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|FSM_Mealy\|state " "Info: Selected Auto state machine encoding method for state machine \"\|FSM_Mealy\|state\"" {  } { { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 12 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|FSM_Mealy\|state " "Info: Encoding result for state machine \"\|FSM_Mealy\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "8 " "Info: Completed encoding using 8 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s7 " "Info: Encoded state bit \"state.s7\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s6 " "Info: Encoded state bit \"state.s6\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s5 " "Info: Encoded state bit \"state.s5\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s4 " "Info: Encoded state bit \"state.s4\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s3 " "Info: Encoded state bit \"state.s3\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s2 " "Info: Encoded state bit \"state.s2\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s1 " "Info: Encoded state bit \"state.s1\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s0 " "Info: Encoded state bit \"state.s0\"" {  } {  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|FSM_Mealy\|state.s0 00000000 " "Info: State \"\|FSM_Mealy\|state.s0\" uses code string \"00000000\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|FSM_Mealy\|state.s1 00000011 " "Info: State \"\|FSM_Mealy\|state.s1\" uses code string \"00000011\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|FSM_Mealy\|state.s2 00000101 " "Info: State \"\|FSM_Mealy\|state.s2\" uses code string \"00000101\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|FSM_Mealy\|state.s3 00001001 " "Info: State \"\|FSM_Mealy\|state.s3\" uses code string \"00001001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|FSM_Mealy\|state.s4 00010001 " "Info: State \"\|FSM_Mealy\|state.s4\" uses code string \"00010001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|FSM_Mealy\|state.s5 00100001 " "Info: State \"\|FSM_Mealy\|state.s5\" uses code string \"00100001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|FSM_Mealy\|state.s6 01000001 " "Info: State \"\|FSM_Mealy\|state.s6\" uses code string \"01000001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|FSM_Mealy\|state.s7 10000001 " "Info: State \"\|FSM_Mealy\|state.s7\" uses code string \"10000001\"" {  } {  } 0}  } { { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 12 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "12 " "Info: Implemented 12 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "9 " "Info: Implemented 9 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 26 21:56:05 2006 " "Info: Processing ended: Mon Jun 26 21:56:05 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}