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📄 fsm_mealy.tan.qmsg

📁 郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register state.s4 zo~reg0 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"state.s4\" and destination register \"zo~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.283 ns + Longest register register " "Info: + Longest register to register delay is 1.283 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.s4 1 REG LC_X6_Y20_N6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y20_N6; Fanout = 2; REG Node = 'state.s4'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "" { state.s4 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.545 ns) + CELL(0.738 ns) 1.283 ns zo~reg0 2 REG LC_X6_Y20_N2 1 " "Info: 2: + IC(0.545 ns) + CELL(0.738 ns) = 1.283 ns; Loc. = LC_X6_Y20_N2; Fanout = 1; REG Node = 'zo~reg0'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "1.283 ns" { state.s4 zo~reg0 } "NODE_NAME" } "" } } { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns 57.52 % " "Info: Total cell delay = 0.738 ns ( 57.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.545 ns 42.48 % " "Info: Total interconnect delay = 0.545 ns ( 42.48 % )" {  } {  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "1.283 ns" { state.s4 zo~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.283 ns" { state.s4 zo~reg0 } { 0.000ns 0.545ns } { 0.000ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_H1 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 9; CLK Node = 'clk'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "" { clk } "NODE_NAME" } "" } } { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns zo~reg0 2 REG LC_X6_Y20_N2 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y20_N2; Fanout = 1; REG Node = 'zo~reg0'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "1.485 ns" { clk zo~reg0 } "NODE_NAME" } "" } } { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "2.954 ns" { clk zo~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 zo~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_H1 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 9; CLK Node = 'clk'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "" { clk } "NODE_NAME" } "" } } { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns state.s4 2 REG LC_X6_Y20_N6 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y20_N6; Fanout = 2; REG Node = 'state.s4'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "1.485 ns" { clk state.s4 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "2.954 ns" { clk state.s4 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 state.s4 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "2.954 ns" { clk zo~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 zo~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "2.954 ns" { clk state.s4 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 state.s4 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 17 -1 0 } }  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "1.283 ns" { state.s4 zo~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.283 ns" { state.s4 zo~reg0 } { 0.000ns 0.545ns } { 0.000ns 0.738ns } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "2.954 ns" { clk zo~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 zo~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "2.954 ns" { clk state.s4 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 state.s4 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "" { zo~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { zo~reg0 } {  } {  } } } { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 17 -1 0 } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "state.s6 xi clk 4.235 ns register " "Info: tsu for register \"state.s6\" (data pin = \"xi\", clock pin = \"clk\") is 4.235 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.152 ns + Longest pin register " "Info: + Longest pin to register delay is 7.152 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns xi 1 PIN PIN_C5 8 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_C5; Fanout = 8; PIN Node = 'xi'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "" { xi } "NODE_NAME" } "" } } { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.199 ns) + CELL(0.478 ns) 7.152 ns state.s6 2 REG LC_X6_Y20_N5 2 " "Info: 2: + IC(5.199 ns) + CELL(0.478 ns) = 7.152 ns; Loc. = LC_X6_Y20_N5; Fanout = 2; REG Node = 'state.s6'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "5.677 ns" { xi state.s6 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.953 ns 27.31 % " "Info: Total cell delay = 1.953 ns ( 27.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.199 ns 72.69 % " "Info: Total interconnect delay = 5.199 ns ( 72.69 % )" {  } {  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "7.152 ns" { xi state.s6 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.152 ns" { xi xi~out0 state.s6 } { 0.000ns 0.000ns 5.199ns } { 0.000ns 1.475ns 0.478ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_H1 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 9; CLK Node = 'clk'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "" { clk } "NODE_NAME" } "" } } { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns state.s6 2 REG LC_X6_Y20_N5 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y20_N5; Fanout = 2; REG Node = 'state.s6'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "1.485 ns" { clk state.s6 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "2.954 ns" { clk state.s6 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 state.s6 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "7.152 ns" { xi state.s6 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.152 ns" { xi xi~out0 state.s6 } { 0.000ns 0.000ns 5.199ns } { 0.000ns 1.475ns 0.478ns } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "2.954 ns" { clk state.s6 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 state.s6 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk zo zo~reg0 6.583 ns register " "Info: tco from clock \"clk\" to destination pin \"zo\" through register \"zo~reg0\" is 6.583 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_H1 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 9; CLK Node = 'clk'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "" { clk } "NODE_NAME" } "" } } { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns zo~reg0 2 REG LC_X6_Y20_N2 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y20_N2; Fanout = 1; REG Node = 'zo~reg0'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "1.485 ns" { clk zo~reg0 } "NODE_NAME" } "" } } { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "2.954 ns" { clk zo~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 zo~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.405 ns + Longest register pin " "Info: + Longest register to pin delay is 3.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns zo~reg0 1 REG LC_X6_Y20_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y20_N2; Fanout = 1; REG Node = 'zo~reg0'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "" { zo~reg0 } "NODE_NAME" } "" } } { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.297 ns) + CELL(2.108 ns) 3.405 ns zo 2 PIN PIN_B5 0 " "Info: 2: + IC(1.297 ns) + CELL(2.108 ns) = 3.405 ns; Loc. = PIN_B5; Fanout = 0; PIN Node = 'zo'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "3.405 ns" { zo~reg0 zo } "NODE_NAME" } "" } } { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 61.91 % " "Info: Total cell delay = 2.108 ns ( 61.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.297 ns 38.09 % " "Info: Total interconnect delay = 1.297 ns ( 38.09 % )" {  } {  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "3.405 ns" { zo~reg0 zo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.405 ns" { zo~reg0 zo } { 0.000ns 1.297ns } { 0.000ns 2.108ns } } }  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "2.954 ns" { clk zo~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 zo~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "3.405 ns" { zo~reg0 zo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.405 ns" { zo~reg0 zo } { 0.000ns 1.297ns } { 0.000ns 2.108ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "state.s0 xi clk -4.173 ns register " "Info: th for register \"state.s0\" (data pin = \"xi\", clock pin = \"clk\") is -4.173 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_H1 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 9; CLK Node = 'clk'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "" { clk } "NODE_NAME" } "" } } { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns state.s0 2 REG LC_X6_Y20_N1 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y20_N1; Fanout = 2; REG Node = 'state.s0'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "1.485 ns" { clk state.s0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "2.954 ns" { clk state.s0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 state.s0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.142 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.142 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns xi 1 PIN PIN_C5 8 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_C5; Fanout = 8; PIN Node = 'xi'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "" { xi } "NODE_NAME" } "" } } { "FSM_Mealy.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/FSM_Mealy.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.189 ns) + CELL(0.478 ns) 7.142 ns state.s0 2 REG LC_X6_Y20_N1 2 " "Info: 2: + IC(5.189 ns) + CELL(0.478 ns) = 7.142 ns; Loc. = LC_X6_Y20_N1; Fanout = 2; REG Node = 'state.s0'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "5.667 ns" { xi state.s0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.953 ns 27.35 % " "Info: Total cell delay = 1.953 ns ( 27.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.189 ns 72.65 % " "Info: Total interconnect delay = 5.189 ns ( 72.65 % )" {  } {  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "7.142 ns" { xi state.s0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.142 ns" { xi xi~out0 state.s0 } { 0.000ns 0.000ns 5.189ns } { 0.000ns 1.475ns 0.478ns } } }  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "2.954 ns" { clk state.s0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 state.s0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy_cmp.qrpt" Compiler "FSM_Mealy" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/db/FSM_Mealy.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Mealy/" "" "7.142 ns" { xi state.s0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.142 ns" { xi xi~out0 state.s0 } { 0.000ns 0.000ns 5.189ns } { 0.000ns 1.475ns 0.478ns } } }  } 0}
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