deccount.tan.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLKIN register lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[1\] register lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[1\] 273.82 MHz 3.652 ns Internal " "Info: Clock \"CLKIN\" has Internal fmax of 273.82 MHz between source register \"lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[1\]\" and destination register \"lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[1\]\" (period= 3.652 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.391 ns + Longest register register " "Info: + Longest register to register delay is 3.391 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[1\] 1 REG LC_X16_Y1_N6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y1_N6; Fanout = 3; REG Node = 'lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[1\]'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 63 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.523 ns) + CELL(0.575 ns) 1.098 ns lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|counter_cella1~COUTCOUT1_1 2 COMB LC_X16_Y1_N6 1 " "Info: 2: + IC(0.523 ns) + CELL(0.575 ns) = 1.098 ns; Loc. = LC_X16_Y1_N6; Fanout = 1; COMB Node = 'lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|counter_cella1~COUTCOUT1_1'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "1.098 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|counter_cella1~COUTCOUT1_1 } "NODE_NAME" } "" } } { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 1.706 ns lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|cout 3 COMB LC_X16_Y1_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 1.706 ns; Loc. = LC_X16_Y1_N7; Fanout = 2; COMB Node = 'lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|cout'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "0.608 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|counter_cella1~COUTCOUT1_1 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|cout } "NODE_NAME" } "" } } { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 88 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.460 ns) + CELL(1.225 ns) 3.391 ns lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[1\] 4 REG LC_X16_Y1_N6 3 " "Info: 4: + IC(0.460 ns) + CELL(1.225 ns) = 3.391 ns; Loc. = LC_X16_Y1_N6; Fanout = 3; REG Node = 'lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[1\]'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "1.685 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|cout lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 63 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.408 ns 71.01 % " "Info: Total cell delay = 2.408 ns ( 71.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.983 ns 28.99 % " "Info: Total interconnect delay = 0.983 ns ( 28.99 % )" {  } {  } 0}  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "3.391 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|counter_cella1~COUTCOUT1_1 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|cout lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.391 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|counter_cella1~COUTCOUT1_1 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|cout lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } { 0.000ns 0.523ns 0.000ns 0.460ns } { 0.000ns 0.575ns 0.608ns 1.225ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN destination 2.903 ns + Shortest register " "Info: + Shortest clock path from clock \"CLKIN\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLKIN 1 CLK PIN_H1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 2; CLK Node = 'CLKIN'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "" { CLKIN } "NODE_NAME" } "" } } { "deccount.vhd" "" { Text "F:/deccount3/deccount.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[1\] 2 REG LC_X16_Y1_N6 3 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X16_Y1_N6; Fanout = 3; REG Node = 'lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[1\]'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "1.434 ns" { CLKIN lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 63 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "2.903 ns" { CLKIN lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { CLKIN CLKIN~out0 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN source 2.903 ns - Longest register " "Info: - Longest clock path from clock \"CLKIN\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLKIN 1 CLK PIN_H1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 2; CLK Node = 'CLKIN'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "" { CLKIN } "NODE_NAME" } "" } } { "deccount.vhd" "" { Text "F:/deccount3/deccount.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[1\] 2 REG LC_X16_Y1_N6 3 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X16_Y1_N6; Fanout = 3; REG Node = 'lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[1\]'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "1.434 ns" { CLKIN lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 63 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "2.903 ns" { CLKIN lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { CLKIN CLKIN~out0 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "2.903 ns" { CLKIN lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { CLKIN CLKIN~out0 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "2.903 ns" { CLKIN lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { CLKIN CLKIN~out0 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 63 8 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 63 8 0 } }  } 0}  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "3.391 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|counter_cella1~COUTCOUT1_1 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|cout lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.391 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|counter_cella1~COUTCOUT1_1 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|cout lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } { 0.000ns 0.523ns 0.000ns 0.460ns } { 0.000ns 0.575ns 0.608ns 1.225ns } } } { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "2.903 ns" { CLKIN lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { CLKIN CLKIN~out0 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "2.903 ns" { CLKIN lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { CLKIN CLKIN~out0 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[1] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLKIN CLKOUT lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[0\] 6.561 ns register " "Info: tco from clock \"CLKIN\" to destination pin \"CLKOUT\" through register \"lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[0\]\" is 6.561 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN source 2.903 ns + Longest register " "Info: + Longest clock path from clock \"CLKIN\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLKIN 1 CLK PIN_H1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 2; CLK Node = 'CLKIN'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "" { CLKIN } "NODE_NAME" } "" } } { "deccount.vhd" "" { Text "F:/deccount3/deccount.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[0\] 2 REG LC_X16_Y1_N5 4 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X16_Y1_N5; Fanout = 4; REG Node = 'lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[0\]'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "1.434 ns" { CLKIN lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 63 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "2.903 ns" { CLKIN lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { CLKIN CLKIN~out0 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 63 8 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.434 ns + Longest register pin " "Info: + Longest register to pin delay is 3.434 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[0\] 1 REG LC_X16_Y1_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y1_N5; Fanout = 4; REG Node = 'lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[0\]'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 63 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.326 ns) + CELL(2.108 ns) 3.434 ns CLKOUT 2 PIN PIN_M8 0 " "Info: 2: + IC(1.326 ns) + CELL(2.108 ns) = 3.434 ns; Loc. = PIN_M8; Fanout = 0; PIN Node = 'CLKOUT'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "3.434 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] CLKOUT } "NODE_NAME" } "" } } { "deccount.vhd" "" { Text "F:/deccount3/deccount.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 61.39 % " "Info: Total cell delay = 2.108 ns ( 61.39 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.326 ns 38.61 % " "Info: Total interconnect delay = 1.326 ns ( 38.61 % )" {  } {  } 0}  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "3.434 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] CLKOUT } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.434 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] CLKOUT } { 0.000ns 1.326ns } { 0.000ns 2.108ns } } }  } 0}  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "2.903 ns" { CLKIN lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { CLKIN CLKIN~out0 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "3.434 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] CLKOUT } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.434 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] CLKOUT } { 0.000ns 1.326ns } { 0.000ns 2.108ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 25 16:24:18 2006 " "Info: Processing ended: Sun Jun 25 16:24:18 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}