deccount.fit.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 25 16:24:09 2006 " "Info: Processing started: Sun Jun 25 16:24:09 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off deccount -c deccount " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off deccount -c deccount" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "deccount EP1C6F256C8 " "Info: Selected device EP1C6F256C8 for design \"deccount\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12F256C8 " "Info: Device EP1C12F256C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "2 2 " "Info: No exact pin location assignment(s) for 2 pins of 2 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLKOUT " "Info: Pin CLKOUT not assigned to an exact location on the device" {  } { { "deccount.vhd" "" { Text "F:/deccount3/deccount.vhd" 10 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLKOUT" } } } } { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "" { CLKOUT } "NODE_NAME" } "" } } { "F:/deccount3/deccount.fld" "" { Floorplan "F:/deccount3/deccount.fld" "" "" { CLKOUT } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLKIN " "Info: Pin CLKIN not assigned to an exact location on the device" {  } { { "deccount.vhd" "" { Text "F:/deccount3/deccount.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLKIN" } } } } { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "" { CLKIN } "NODE_NAME" } "" } } { "F:/deccount3/deccount.fld" "" { Floorplan "F:/deccount3/deccount.fld" "" "" { CLKIN } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLKIN Global clock in PIN H1 " "Info: Automatically promoted signal \"CLKIN\" to use Global clock in PIN H1" {  } { { "deccount.vhd" "" { Text "F:/deccount3/deccount.vhd" 9 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.30 0 1 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 41 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  41 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 48 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 45 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 48 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.394 ns register register " "Info: Estimated most critical path is register to register delay of 3.394 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[0\] 1 REG LAB_X16_Y1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X16_Y1; Fanout = 4; REG Node = 'lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[0\]'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 63 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.470 ns) + CELL(0.575 ns) 1.045 ns lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|counter_cella0~COUTCOUT1 2 COMB LAB_X16_Y1 2 " "Info: 2: + IC(0.470 ns) + CELL(0.575 ns) = 1.045 ns; Loc. = LAB_X16_Y1; Fanout = 2; COMB Node = 'lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|counter_cella0~COUTCOUT1'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "1.045 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|counter_cella0~COUTCOUT1 } "NODE_NAME" } "" } } { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 34 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.125 ns lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|counter_cella1~COUTCOUT1_1 3 COMB LAB_X16_Y1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.125 ns; Loc. = LAB_X16_Y1; Fanout = 1; COMB Node = 'lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|counter_cella1~COUTCOUT1_1'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "0.080 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|counter_cella0~COUTCOUT1 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|counter_cella1~COUTCOUT1_1 } "NODE_NAME" } "" } } { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 1.733 ns lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|cout 4 COMB LAB_X16_Y1 2 " "Info: 4: + IC(0.000 ns) + CELL(0.608 ns) = 1.733 ns; Loc. = LAB_X16_Y1; Fanout = 2; COMB Node = 'lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|cout'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "0.608 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|counter_cella1~COUTCOUT1_1 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|cout } "NODE_NAME" } "" } } { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 88 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(1.225 ns) 3.394 ns lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[0\] 5 REG LAB_X16_Y1 4 " "Info: 5: + IC(0.436 ns) + CELL(1.225 ns) = 3.394 ns; Loc. = LAB_X16_Y1; Fanout = 4; REG Node = 'lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\|safe_q\[0\]'" {  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "1.661 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|cout lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 63 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.488 ns 73.31 % " "Info: Total cell delay = 2.488 ns ( 73.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.906 ns 26.69 % " "Info: Total interconnect delay = 0.906 ns ( 26.69 % )" {  } {  } 0}  } { { "F:/deccount3/db/deccount_cmp.qrpt" "" { Report "F:/deccount3/db/deccount_cmp.qrpt" Compiler "deccount" "UNKNOWN" "V1" "F:/deccount3/db/deccount.quartus_db" { Floorplan "F:/deccount3/" "" "3.394 ns" { lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|counter_cella0~COUTCOUT1 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|counter_cella1~COUTCOUT1_1 lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|cout lpm_counter:lpm_counter_component|cntr_ia8:auto_generated|safe_q[0] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 25 16:24:12 2006 " "Info: Processing ended: Sun Jun 25 16:24:12 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}