deccount.map.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 25 16:24:05 2006 " "Info: Processing started: Sun Jun 25 16:24:05 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off deccount -c deccount " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off deccount -c deccount" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "deccount.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file deccount.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 deccount-behavioural " "Info: Found design unit 1: deccount-behavioural" {  } { { "deccount.vhd" "" { Text "F:/deccount3/deccount.vhd" 18 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 deccount " "Info: Found entity 1: deccount" {  } { { "deccount.vhd" "" { Text "F:/deccount3/deccount.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "deccount " "Info: Elaborating entity \"deccount\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"lpm_counter:lpm_counter_component\"" {  } { { "deccount.vhd" "lpm_counter_component" { Text "F:/deccount3/deccount.vhd" 52 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ia8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_ia8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ia8 " "Info: Found entity 1: cntr_ia8" {  } { { "db/cntr_ia8.tdf" "" { Text "F:/deccount3/db/cntr_ia8.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_ia8 lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated " "Info: Elaborating entity \"cntr_ia8\" for hierarchy \"lpm_counter:lpm_counter_component\|cntr_ia8:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 251 3 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "6 " "Info: Implemented 6 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "4 " "Info: Implemented 4 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 25 16:24:07 2006 " "Info: Processing ended: Sun Jun 25 16:24:07 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}