standard_1c6.v

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

  input            cpu_0_data_master_read_data_valid_led_s1;
  input            cpu_0_data_master_read_data_valid_p0_7_p0_30_s1;
  input            cpu_0_data_master_read_data_valid_p1_16_p1_25_s1;
  input            cpu_0_data_master_read_data_valid_p2_16_p2_31_s1;
  input            cpu_0_data_master_read_data_valid_pwm_control_slave;
  input            cpu_0_data_master_read_data_valid_sdram_s1;
  input   [  6: 0] cpu_0_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_0_data_master_read_data_valid_spi_spi_control_port;
  input            cpu_0_data_master_read_data_valid_sys_clock_timer_s1;
  input            cpu_0_data_master_read_data_valid_sysid_control_slave;
  input            cpu_0_data_master_read_data_valid_uart_s1;
  input            cpu_0_data_master_read_data_valid_watchdog_s1;
  input            cpu_0_data_master_requests_CF_IDE_s1;
  input            cpu_0_data_master_requests_DM9000_s1;
  input            cpu_0_data_master_requests_PACK_s1;
  input            cpu_0_data_master_requests_S1D13503_Memory_s1;
  input            cpu_0_data_master_requests_S1D13503_Register_s1;
  input            cpu_0_data_master_requests_cpu_0_jtag_debug_module;
  input            cpu_0_data_master_requests_epcs_controller_epcs_control_port;
  input            cpu_0_data_master_requests_ext_Flash_s1;
  input            cpu_0_data_master_requests_high_res_timer_s1;
  input            cpu_0_data_master_requests_i2c_master_s1;
  input            cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave;
  input            cpu_0_data_master_requests_k9f2808u0c_avalon_tristate_slave;
  input            cpu_0_data_master_requests_led_s1;
  input            cpu_0_data_master_requests_p0_7_p0_30_s1;
  input            cpu_0_data_master_requests_p1_16_p1_25_s1;
  input            cpu_0_data_master_requests_p2_16_p2_31_s1;
  input            cpu_0_data_master_requests_pwm_control_slave;
  input            cpu_0_data_master_requests_sdram_s1;
  input            cpu_0_data_master_requests_spi_spi_control_port;
  input            cpu_0_data_master_requests_sys_clock_timer_s1;
  input            cpu_0_data_master_requests_sysid_control_slave;
  input            cpu_0_data_master_requests_uart_s1;
  input            cpu_0_data_master_requests_watchdog_s1;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input   [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
  input            d1_cpu_0_jtag_debug_module_end_xfer;
  input            d1_epcs_controller_epcs_control_port_end_xfer;
  input            d1_ext_mem_bus_avalon_slave_end_xfer;
  input            d1_high_res_timer_s1_end_xfer;
  input            d1_i2c_master_s1_end_xfer;
  input            d1_jtag_uart_avalon_jtag_slave_end_xfer;
  input            d1_led_s1_end_xfer;
  input            d1_nand_flash_bus_avalon_slave_end_xfer;
  input            d1_p0_7_p0_30_s1_end_xfer;
  input            d1_p1_16_p1_25_s1_end_xfer;
  input            d1_p2_16_p2_31_s1_end_xfer;
  input            d1_pwm_control_slave_end_xfer;
  input            d1_sdram_s1_end_xfer;
  input            d1_spi_spi_control_port_end_xfer;
  input            d1_sys_clock_timer_s1_end_xfer;
  input            d1_sysid_control_slave_end_xfer;
  input            d1_uart_s1_end_xfer;
  input            d1_watchdog_s1_end_xfer;
  input            epcs_controller_epcs_control_port_irq_from_sa;
  input   [ 31: 0] epcs_controller_epcs_control_port_readdata_from_sa;
  input            ext_Flash_s1_wait_counter_eq_0;
  input            ext_Flash_s1_wait_counter_eq_1;
  input            high_res_timer_s1_irq_from_sa;
  input   [ 15: 0] high_res_timer_s1_readdata_from_sa;
  input            i2c_master_s1_irq_from_sa;
  input   [ 31: 0] i2c_master_s1_readdata_from_sa;
  input            i2c_master_s1_waitrequest_n_from_sa;
  input   [ 15: 0] incoming_ext_mem_bus_data_with_Xs_converted_to_0;
  input   [  7: 0] incoming_nand_flash_bus_data;
  input            jtag_uart_avalon_jtag_slave_irq_from_sa;
  input   [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  input            jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  input            k9f2808u0c_avalon_tristate_slave_wait_counter_eq_0;
  input            k9f2808u0c_avalon_tristate_slave_wait_counter_eq_1;
  input            p0_7_p0_30_s1_irq_from_sa;
  input   [ 23: 0] p0_7_p0_30_s1_readdata_from_sa;
  input            p1_16_p1_25_s1_irq_from_sa;
  input   [  9: 0] p1_16_p1_25_s1_readdata_from_sa;
  input            p2_16_p2_31_s1_irq_from_sa;
  input   [ 15: 0] p2_16_p2_31_s1_readdata_from_sa;
  input   [ 31: 0] pwm_control_slave_readdata_from_sa;
  input            registered_cpu_0_data_master_read_data_valid_CF_IDE_s1;
  input            registered_cpu_0_data_master_read_data_valid_DM9000_s1;
  input            registered_cpu_0_data_master_read_data_valid_PACK_s1;
  input            registered_cpu_0_data_master_read_data_valid_S1D13503_Memory_s1;
  input            registered_cpu_0_data_master_read_data_valid_S1D13503_Register_s1;
  input            registered_cpu_0_data_master_read_data_valid_ext_Flash_s1;
  input            registered_cpu_0_data_master_read_data_valid_k9f2808u0c_avalon_tristate_slave;
  input            reset_n;
  input   [  6: 0] sdram_s1_posted_fifo_readenable;
  input   [  6: 0] sdram_s1_posted_fifo_writenable;
  input   [ 15: 0] sdram_s1_readdata_from_sa;
  input            sdram_s1_waitrequest_from_sa;
  input            spi_spi_control_port_irq_from_sa;
  input   [ 15: 0] spi_spi_control_port_readdata_from_sa;
  input            sys_clock_timer_s1_irq_from_sa;
  input   [ 15: 0] sys_clock_timer_s1_readdata_from_sa;
  input   [ 31: 0] sysid_control_slave_readdata_from_sa;
  input            uart_s1_irq_from_sa;
  input   [ 15: 0] uart_s1_readdata_from_sa;
  input            watchdog_s1_irq_from_sa;
  input   [ 15: 0] watchdog_s1_readdata_from_sa;

  wire    [ 26: 0] cpu_0_data_master_address_to_slave;
  reg     [  1: 0] cpu_0_data_master_dbs_address;
  wire    [  1: 0] cpu_0_data_master_dbs_increment;
  wire    [ 15: 0] cpu_0_data_master_dbs_write_16;
  wire    [ 31: 0] cpu_0_data_master_irq;
  reg              cpu_0_data_master_no_byte_enables_and_last_term;
  wire    [ 31: 0] cpu_0_data_master_readdata;
  wire             cpu_0_data_master_run;
  reg              cpu_0_data_master_waitrequest;
  reg     [ 15: 0] dbs_16_reg_segment_0;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  wire             dummy_sink;
  wire             last_dbs_term_and_run;
  wire    [  1: 0] next_dbs_address;
  wire    [ 15: 0] p1_dbs_16_reg_segment_0;
  wire    [ 31: 0] p1_registered_cpu_0_data_master_readdata;
  wire             pre_dbs_count_enable;
  wire             r_0;
  wire             r_1;
  wire             r_2;
  wire             r_3;
  wire             r_4;
  reg     [ 31: 0] registered_cpu_0_data_master_readdata;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_data_master_requests_cpu_0_jtag_debug_module) & (cpu_0_data_master_granted_cpu_0_jtag_debug_module | ~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module) & ((~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_data_master_write | (1 & 1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_epcs_controller_epcs_control_port | ~cpu_0_data_master_requests_epcs_controller_epcs_control_port) & (cpu_0_data_master_granted_epcs_controller_epcs_control_port | ~cpu_0_data_master_qualified_request_epcs_controller_epcs_control_port) & ((~cpu_0_data_master_qualified_request_epcs_controller_epcs_control_port | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_epcs_controller_epcs_control_port | ~cpu_0_data_master_write | (1 & 1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_CF_IDE_s1 | registered_cpu_0_data_master_read_data_valid_CF_IDE_s1 | ~cpu_0_data_master_requests_CF_IDE_s1) & (cpu_0_data_master_qualified_request_DM9000_s1 | registered_cpu_0_data_master_read_data_valid_DM9000_s1 | ~cpu_0_data_master_requests_DM9000_s1) & (cpu_0_data_master_qualified_request_S1D13503_Register_s1 | registered_cpu_0_data_master_read_data_valid_S1D13503_Register_s1 | ~cpu_0_data_master_requests_S1D13503_Register_s1) & (cpu_0_data_master_qualified_request_ext_Flash_s1 | (registered_cpu_0_data_master_read_data_valid_ext_Flash_s1 & cpu_0_data_master_dbs_address[1]) | (cpu_0_data_master_write & !cpu_0_data_master_byteenable_ext_Flash_s1 & cpu_0_data_master_dbs_address[1]) | ~cpu_0_data_master_requests_ext_Flash_s1) & (cpu_0_data_master_qualified_request_S1D13503_Memory_s1 | registered_cpu_0_data_master_read_data_valid_S1D13503_Memory_s1 | ~cpu_0_data_master_requests_S1D13503_Memory_s1) & (cpu_0_data_master_qualified_request_PACK_s1 | registered_cpu_0_data_master_read_data_valid_PACK_s1 | ~cpu_0_data_master_requests_PACK_s1) & (cpu_0_data_master_granted_CF_IDE_s1 | ~cpu_0_data_master_qualified_request_CF_IDE_s1) & (cpu_0_data_master_granted_DM9000_s1 | ~cpu_0_data_master_qualified_request_DM9000_s1) & (cpu_0_data_master_granted_S1D13503_Register_s1 | ~cpu_0_data_master_qualified_request_S1D13503_Register_s1);

  //cascaded wait assignment, which is an e_assign
  assign cpu_0_data_master_run = r_0 & r_1 & r_2 & r_3 & r_4;

  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = (cpu_0_data_master_granted_ext_Flash_s1 | ~cpu_0_data_master_qualified_request_ext_Flash_s1) & (cpu_0_data_master_granted_S1D13503_Memory_s1 | ~cpu_0_data_master_qualified_request_S1D13503_Memory_s1) & (cpu_0_data_master_granted_PACK_s1 | ~cpu_0_data_master_qualified_request_PACK_s1) & ((~cpu_0_data_master_qualified_request_CF_IDE_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_CF_IDE_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_CF_IDE_s1 | ~cpu_0_data_master_write | (1 & CF_IDE_s1_wait_counter_eq_1 & cpu_0_data_master_write))) & ((~cpu_0_data_master_qualified_request_DM9000_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_DM9000_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_DM9000_s1 | ~cpu_0_data_master_write | (1 & DM9000_s1_wait_counter_eq_1 & cpu_0_data_master_write))) & ((~cpu_0_data_master_qualified_request_S1D13503_Register_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_S1D13503_Register_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_S1D13503_Register_s1 | ~cpu_0_data_master_write | (1 & S1D13503_Register_s1_wait_counter_eq_1 & cpu_0_data_master_write))) & ((~cpu_0_data_master_qualified_request_ext_Flash_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_ext_Flash_s1 & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_ext_Flash_s1 | ~cpu_0_data_master_write | (1 & ext_Flash_s1_wait_counter_eq_1 & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_write))) & ((~cpu_0_data_master_qualified_request_S1D13503_Memory_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_S1D13503_Memory_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_S1D13503_Memory_s1 | ~cpu_0_data_master_write | (1 & S1D13503_Memory_s1_wait_counter_eq_1 & cpu_0_data_master_write))) & ((~cpu_0_data_master_qualified_request_PACK_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_PACK_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_PACK_s1 | ~cpu_0_data_master_write | (1 & PACK_s1_wait_counter_eq_1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_high_res_timer_s1 | ~cpu_0_data_master_requests_high_res_timer_s1) & ((~cpu_0_data_master_qualified_request_high_res_timer_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_high_res_timer_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1;

  //r_2 master_run cascaded wait assignment, which is an e_assign
  assign r_2 = (cpu_0_data_master_qualified_request_i2c_master_s1 | ~cpu_0_data_master_requests_i2c_master_s1) & ((~cpu_0_data_master_qualified_request_i2c_master_s1 | ~cpu_0_data_master_read | (1 & i2c_master_s1_waitrequest_n_from_sa & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_i2c_master_s1 | ~cpu_0_data_master_write | (1 & i2c_master_s1_waitrequest_n_from_sa & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave) & ((~cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~cpu_0_data_master_read | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~cpu_0_data_master_write | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_led_s1 | ~cpu_0_data_master_requests_led_s1) & ((~cpu_0_data_master_qualified_request_led_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_led_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_k9f2808u0c_avalon_tristate_slave | registered_cpu_0_data_master_read_data_valid_k9f2808u0c_avalon_tristate_slave | ~cpu_0_data_master_requests_k9f2808u0c_avalon_tristate_slave) & (cpu_0_data_master_granted_k9f2808u0c_avalon_tristate_slave | ~cpu_0_data_master_qualified_request_k9f2808u0c_avalon_tristate_slave) & ((~cpu_0_data_master_qualified_request_k9f2808u0c_avalon_tristate_slave | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_k9f2808u0c_avalon_tristate_slave & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_k9f2808u0c_avalon_tristate_slave | ~cpu_0_data_master_write | (1 & k9f2808u0c_avalon_tristate_slave_wait_counter_eq_1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_p0_7_p0_30_s1 | ~cpu_0_data_master_requests_p0_7_p0_30_s1) & ((~cpu_0_data_master_qualified_request_p0_7_p0_30_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_p0_7_p0_30_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write)));

  //r_3 master_run cascaded wait assignment, which is an e_assign
  assign r_3 = 1 & (cpu_0_data_master_qualified_request_p1_16_p1_25_s1 | ~cpu_0_data_master_requests_p1_16_p1_25_s1) & ((~cpu_0_data_master_qualified_request_p1_16_p1_25_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_p1_16_p1_25_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_p2_16_p2_31_s1 | ~cpu_0_data_master_requests_p2_16_p2_31_s1) & ((~cpu_0_data_master_qualified_request_p2_16_p2_31_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_p2_16_p2_31_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_pwm_control_slave | ~cpu_0_data_master_requests_pwm_control_slave) & ((~cpu_0_data_master_qualified_request_pwm_control_slave | ~cpu_0_data_master_read | (1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_pwm_control_slave | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_sdram_s1 | (cpu_0_data_master_read_data_valid_sdram_s1 & cpu_0_data_master_dbs_address[1]) | (cpu_0_data_master_write & !cpu_0_data_master_byteenable_sdram_s1 & cpu_0_data_master_dbs_address[1]) | ~cpu_0_data_master_requests_sdram_s1) & (cpu_0_data_master_granted_sdram_s1 | ~cpu_0_data_master_qualified_request_sdram_s1) & ((~cpu_0_data_master_qualified_request_sdram_s1 | ~cpu_0_data_master_read | (cpu_0_data_master_read_data_valid_sdram_s1 & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_sdram_s1 | ~cpu_0_data_master_write | (1 & ~sdram_s1_waitrequest_from_sa & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_write))) & 1 & ((~cpu_0_data_master_qualified_request_spi_spi_control_port | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_spi_spi_control_port | ~cpu_0_data_master_write | (1 & 1 & cpu_0_data_master_write)));

  //r_4 master_run cascaded wait assignment, which is an e_assign
  assign r_4 = 1 & (cpu_0_data_master_qualified_request_sys_clock_timer_s1 | ~cpu_0_data_master_requests_sys_clock_timer_s1) & ((~cpu_0_data_master_qualified_request_sys_clock_timer_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_sys_clock_timer_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & ((~cpu_0_data_master_qualified_request_sysid_control_slave | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_sysid_control_slave | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & ((~cpu_0_data_master_qualified_request_uart_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_uart_s1 | ~cpu_0_data_master_write | (1 & 1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_watchdog_s1 | ~cpu_0_data_master_requests_watchdog_s1) & ((~cpu_0_data_master_qualified_request_watchdog_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_watchdog_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write)));

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_0_data_master_address_to_slave = cpu_0_data_master_address[26 : 0];

  //cpu_0/data_master readdata mux, which is an e_mux
  assign cpu_0_data_master_readdata = ({32 {~cpu_0_data_master_requests_cpu_0_jtag_debug_module}} | cpu_0_jtag_debug_module_readdata_from_sa) &
    ({32 {~cpu_0_data_master_requests_epcs_controller_epcs_control_port}} | epcs_controller_epcs_control_port_readdata_from_sa) &
    ({32 {~cpu_0_data_master_requests_CF_IDE_s1}} | incoming_ext_mem_bus_data_with_Xs_converted_to_0) &
    ({32 {~cpu_0_data_master_requests_DM9000_s1}} | incoming_ext_mem_bus_data_with_Xs_converted_to_0) &
    ({32 {~cpu_0_data_master_requests_S1D13503_Register_s1}} | incoming_ext_mem_bus_data_with_Xs_converted_to_0) &
    ({32 {~cpu_0_data_master_requests_ext_Flash_s1}} | {incoming_ext_mem_bus_data_with_Xs_converted_to_0,
    dbs_16_reg_segment_0}) &
    ({32 {~cpu_0_data_master_requests_S1D13503_Memory_s1}} | incoming_ext_mem_bus_data_with_Xs_converted_to_0) &
    ({32 {~cpu_0_data_master_requests_PACK_s1}} | incoming_ext_mem_bus_data_with_Xs_converted_to_0) &
    ({32 {~cpu_0_data_master_requests_high_res_timer_s1}} | high_res_timer_s1_readdata_from_sa) &
    ({32 {~cpu_0_data_master_requests_i2c_master_s1}} | registered_cpu_0_data_master_readdata) &
    ({32 {~cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave}} | registered_cpu_0_data_master_readdata) &
    ({32 {~cpu_0_data_master_requests_k9f2808u0c_avalon_tristate_slave}} | incoming_nand_flash_bus_data) &
    ({32 {~cpu_0_data_master_requests_p0_7_p0_30_s1}} | p0_7_p0_30_s1_readdata_from_sa) &
    ({32 {~cpu_0_data_master_requests_p1_16_p1_25_s1}} | p1_16_p1_25_s1_readdata_from_sa) &
    ({32 {~cpu_0_data_master_requests_p2_16_p2_31_s1}} | p2_16_p2_31_s1_readdata_from_sa) &
    ({32 {~cpu_0_data_master_requests_pwm_control_slave}} | registered_cpu_0_data_master_readdata) &
    ({32 {~cpu_0_data_master_requests_sdram_s1}} | registered_cpu_0_data_master_readdata) &
    ({32 {~cpu_0_data_master_requests_spi_spi_control_port}} | spi_spi_control_port_readdata_from_sa) &
    ({32 {~cpu_0_data_master_reque