standard_1c6.v

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

    begin
      if (reset_n == 0)
          d1_cpu_0_jtag_debug_module_end_xfer <= 1;
      else if (1)
          d1_cpu_0_jtag_debug_module_end_xfer <= cpu_0_jtag_debug_module_end_xfer;
    end


  //cpu_0_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
  assign cpu_0_jtag_debug_module_waits_for_read = cpu_0_jtag_debug_module_in_a_read_cycle & cpu_0_jtag_debug_module_begins_xfer;

  //cpu_0_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
  assign cpu_0_jtag_debug_module_in_a_read_cycle = (cpu_0_data_master_granted_cpu_0_jtag_debug_module & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_cpu_0_jtag_debug_module & cpu_0_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = cpu_0_jtag_debug_module_in_a_read_cycle;

  //cpu_0_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
  assign cpu_0_jtag_debug_module_waits_for_write = cpu_0_jtag_debug_module_in_a_write_cycle & cpu_0_jtag_debug_module_begins_xfer;

  //cpu_0_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
  assign cpu_0_jtag_debug_module_in_a_write_cycle = cpu_0_data_master_granted_cpu_0_jtag_debug_module & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = cpu_0_jtag_debug_module_in_a_write_cycle;

  assign wait_for_cpu_0_jtag_debug_module_counter = 0;
  //cpu_0_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
  assign cpu_0_jtag_debug_module_byteenable = (cpu_0_data_master_granted_cpu_0_jtag_debug_module)? cpu_0_data_master_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_granted_cpu_0_jtag_debug_module + cpu_0_instruction_master_granted_cpu_0_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module + cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

  // synthesis attribute cpu_0_jtag_debug_module_arbitrator auto_dissolve FALSE

endmodule


module cpu_0_data_master_arbitrator (
                                      // inputs:
                                       CF_IDE_s1_wait_counter_eq_0,
                                       CF_IDE_s1_wait_counter_eq_1,
                                       DM9000_s1_wait_counter_eq_0,
                                       DM9000_s1_wait_counter_eq_1,
                                       PACK_s1_wait_counter_eq_0,
                                       PACK_s1_wait_counter_eq_1,
                                       S1D13503_Memory_s1_wait_counter_eq_0,
                                       S1D13503_Memory_s1_wait_counter_eq_1,
                                       S1D13503_Register_s1_wait_counter_eq_0,
                                       S1D13503_Register_s1_wait_counter_eq_1,
                                       clk,
                                       cpu_0_data_master_address,
                                       cpu_0_data_master_byteenable_ext_Flash_s1,
                                       cpu_0_data_master_byteenable_sdram_s1,
                                       cpu_0_data_master_debugaccess,
                                       cpu_0_data_master_granted_CF_IDE_s1,
                                       cpu_0_data_master_granted_DM9000_s1,
                                       cpu_0_data_master_granted_PACK_s1,
                                       cpu_0_data_master_granted_S1D13503_Memory_s1,
                                       cpu_0_data_master_granted_S1D13503_Register_s1,
                                       cpu_0_data_master_granted_cpu_0_jtag_debug_module,
                                       cpu_0_data_master_granted_epcs_controller_epcs_control_port,
                                       cpu_0_data_master_granted_ext_Flash_s1,
                                       cpu_0_data_master_granted_high_res_timer_s1,
                                       cpu_0_data_master_granted_i2c_master_s1,
                                       cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave,
                                       cpu_0_data_master_granted_k9f2808u0c_avalon_tristate_slave,
                                       cpu_0_data_master_granted_led_s1,
                                       cpu_0_data_master_granted_p0_7_p0_30_s1,
                                       cpu_0_data_master_granted_p1_16_p1_25_s1,
                                       cpu_0_data_master_granted_p2_16_p2_31_s1,
                                       cpu_0_data_master_granted_pwm_control_slave,
                                       cpu_0_data_master_granted_sdram_s1,
                                       cpu_0_data_master_granted_spi_spi_control_port,
                                       cpu_0_data_master_granted_sys_clock_timer_s1,
                                       cpu_0_data_master_granted_sysid_control_slave,
                                       cpu_0_data_master_granted_uart_s1,
                                       cpu_0_data_master_granted_watchdog_s1,
                                       cpu_0_data_master_qualified_request_CF_IDE_s1,
                                       cpu_0_data_master_qualified_request_DM9000_s1,
                                       cpu_0_data_master_qualified_request_PACK_s1,
                                       cpu_0_data_master_qualified_request_S1D13503_Memory_s1,
                                       cpu_0_data_master_qualified_request_S1D13503_Register_s1,
                                       cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module,
                                       cpu_0_data_master_qualified_request_epcs_controller_epcs_control_port,
                                       cpu_0_data_master_qualified_request_ext_Flash_s1,
                                       cpu_0_data_master_qualified_request_high_res_timer_s1,
                                       cpu_0_data_master_qualified_request_i2c_master_s1,
                                       cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
                                       cpu_0_data_master_qualified_request_k9f2808u0c_avalon_tristate_slave,
                                       cpu_0_data_master_qualified_request_led_s1,
                                       cpu_0_data_master_qualified_request_p0_7_p0_30_s1,
                                       cpu_0_data_master_qualified_request_p1_16_p1_25_s1,
                                       cpu_0_data_master_qualified_request_p2_16_p2_31_s1,
                                       cpu_0_data_master_qualified_request_pwm_control_slave,
                                       cpu_0_data_master_qualified_request_sdram_s1,
                                       cpu_0_data_master_qualified_request_spi_spi_control_port,
                                       cpu_0_data_master_qualified_request_sys_clock_timer_s1,
                                       cpu_0_data_master_qualified_request_sysid_control_slave,
                                       cpu_0_data_master_qualified_request_uart_s1,
                                       cpu_0_data_master_qualified_request_watchdog_s1,
                                       cpu_0_data_master_read,
                                       cpu_0_data_master_read_data_valid_CF_IDE_s1,
                                       cpu_0_data_master_read_data_valid_DM9000_s1,
                                       cpu_0_data_master_read_data_valid_PACK_s1,
                                       cpu_0_data_master_read_data_valid_S1D13503_Memory_s1,
                                       cpu_0_data_master_read_data_valid_S1D13503_Register_s1,
                                       cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module,
                                       cpu_0_data_master_read_data_valid_epcs_controller_epcs_control_port,
                                       cpu_0_data_master_read_data_valid_ext_Flash_s1,
                                       cpu_0_data_master_read_data_valid_high_res_timer_s1,
                                       cpu_0_data_master_read_data_valid_i2c_master_s1,
                                       cpu_0_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
                                       cpu_0_data_master_read_data_valid_k9f2808u0c_avalon_tristate_slave,
                                       cpu_0_data_master_read_data_valid_led_s1,
                                       cpu_0_data_master_read_data_valid_p0_7_p0_30_s1,
                                       cpu_0_data_master_read_data_valid_p1_16_p1_25_s1,
                                       cpu_0_data_master_read_data_valid_p2_16_p2_31_s1,
                                       cpu_0_data_master_read_data_valid_pwm_control_slave,
                                       cpu_0_data_master_read_data_valid_sdram_s1,
                                       cpu_0_data_master_read_data_valid_sdram_s1_shift_register,
                                       cpu_0_data_master_read_data_valid_spi_spi_control_port,
                                       cpu_0_data_master_read_data_valid_sys_clock_timer_s1,
                                       cpu_0_data_master_read_data_valid_sysid_control_slave,
                                       cpu_0_data_master_read_data_valid_uart_s1,
                                       cpu_0_data_master_read_data_valid_watchdog_s1,
                                       cpu_0_data_master_requests_CF_IDE_s1,
                                       cpu_0_data_master_requests_DM9000_s1,
                                       cpu_0_data_master_requests_PACK_s1,
                                       cpu_0_data_master_requests_S1D13503_Memory_s1,
                                       cpu_0_data_master_requests_S1D13503_Register_s1,
                                       cpu_0_data_master_requests_cpu_0_jtag_debug_module,
                                       cpu_0_data_master_requests_epcs_controller_epcs_control_port,
                                       cpu_0_data_master_requests_ext_Flash_s1,
                                       cpu_0_data_master_requests_high_res_timer_s1,
                                       cpu_0_data_master_requests_i2c_master_s1,
                                       cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave,
                                       cpu_0_data_master_requests_k9f2808u0c_avalon_tristate_slave,
                                       cpu_0_data_master_requests_led_s1,