pwm.v

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

//Legal Notice: (C)2005 Altera Corporation. All rights reserved.  Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.

// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module pwm (
             // inputs:
              address,
              avalon_chip_select,
              clk,
              read,
              resetn,
              write,
              write_data,

             // outputs:
              pwm_out,
              read_data
           );

  output           pwm_out;
  output  [ 31: 0] read_data;
  input   [  1: 0] address;
  input            avalon_chip_select;
  input            clk;
  input            read;
  input            resetn;
  input            write;
  input   [ 31: 0] write_data;

  wire             pwm_out;
  wire    [ 31: 0] read_data;
  pwm_avalon_interface the_pwm_avalon_interface
    (
      .address            (address),
      .avalon_chip_select (avalon_chip_select),
      .clk                (clk),
      .pwm_out            (pwm_out),
      .read               (read),
      .read_data          (read_data),
      .resetn             (resetn),
      .write              (write),
      .write_data         (write_data)
    );
  defparam the_pwm_avalon_interface.clock_divide_reg_init = 0,
           the_pwm_avalon_interface.duty_cycle_reg_init = 0;



endmodule