standard.fit.rpt

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

+--------------------------------------------------------------------------+
; Fitter Summary                                                           ;
+-----------------------+--------------------------------------------------+
; Fitter Status         ; Successful - Fri Oct 28 18:17:35 2005            ;
; Quartus II Version    ; 5.0 Build 168 06/22/2005 SP 1.04 SJ Full Version ;
; Revision Name         ; standard                                         ;
; Top-level Entity Name ; standard                                         ;
; Family                ; Cyclone                                          ;
; Device                ; EP1C6F256C8                                      ;
; Timing Models         ; Final                                            ;
; Total logic elements  ; 4,785 / 5,980 ( 80 % )                           ;
; Total pins            ; 165 / 185 ( 89 % )                               ;
; Total virtual pins    ; 0                                                ;
; Total memory bits     ; 33,280 / 92,160 ( 36 % )                         ;
; Total PLLs            ; 1 / 2 ( 50 % )                                   ;
+-----------------------+--------------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                          ;
+----------------------------------------------------+--------------------+--------------------------------+
; Option                                             ; Setting            ; Default Value                  ;
+----------------------------------------------------+--------------------+--------------------------------+
; Device                                             ; EP1C6F256C8        ;                                ;
; Optimize Hold Timing                               ; All paths          ; IO Paths and Minimum TPD Paths ;
; Use smart compilation                              ; Off                ; Off                            ;
; Placement Effort Multiplier                        ; 1.0                ; 1.0                            ;
; Router Effort Multiplier                           ; 1.0                ; 1.0                            ;
; Optimize Fast-Corner Timing                        ; Off                ; Off                            ;
; Optimize Timing                                    ; Normal compilation ; Normal compilation             ;
; Optimize IOC Register Placement for Timing         ; On                 ; On                             ;
; Limit to One Fitting Attempt                       ; Off                ; Off                            ;
; Final Placement Optimizations                      ; Automatically      ; Automatically                  ;
; Fitter Initial Placement Seed                      ; 1                  ; 1                              ;
; Slow Slew Rate                                     ; Off                ; Off                            ;
; PCI I/O                                            ; Off                ; Off                            ;
; Weak Pull-Up Resistor                              ; Off                ; Off                            ;
; Enable Bus-Hold Circuitry                          ; Off                ; Off                            ;
; Auto Global Memory Control Signals                 ; Off                ; Off                            ;
; Auto Packed Registers -- Cyclone                   ; Auto               ; Auto                           ;
; Auto Delay Chains                                  ; On                 ; On                             ;
; Auto Merge PLLs                                    ; On                 ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                ; Off                            ;
; Perform Register Duplication                       ; Off                ; Off                            ;
; Perform Register Retiming                          ; Off                ; Off                            ;
; Fitter Effort                                      ; Auto Fit           ; Auto Fit                       ;
; Physical Synthesis Effort Level                    ; Normal             ; Normal                         ;
; Logic Cell Insertion - Logic Duplication           ; Auto               ; Auto                           ;
; Auto Register Duplication                          ; Off                ; Off                            ;
; Auto Global Clock                                  ; On                 ; On                             ;
; Auto Global Register Control Signals               ; On                 ; On                             ;
+----------------------------------------------------+--------------------+--------------------------------+


+----------------------------------------------------------------------------------------+
; Fitter Device Options                                                                  ;