class.ptf

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

                  }
                  PORT read
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "read";
                    is_shared = "0";
                  }
                  PORT read_data
                  {
                    width = "32";
                    width_expression = "";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT pwm_out
                  {
                    width = "1";
                    width_expression = "";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                }
              }
            }
            USER_INTERFACE 
            {
              USER_LABELS 
              {
                name = "pwm_avalon_interface";
                technology = "imported components";
              }
            }
            CB_GENERATOR 
            {
              top_module_name = "pwm_avalon_interface";
              emit_system_h = "0";
              HDL_FILES 
              {
                FILE 
                {
                  filepath = "D:/QProj/CC/pwm_source/pwm_hw/pwm_avalon_interface.v";
                  use_in_simulation = "1";
                  use_in_synthesis = "1";
                }
              }
            }
            SOPC_Builder_Version = "0.0";
            COMPONENT_BUILDER 
            {
              HDL_PARAMETERS 
              {
                # generated by cbDocument.CBDocument.getParameterContainer:385
                # used only by Component Editor
                HDL_PARAMETER clock_divide_reg_init
                {
                  parameter_name = "clock_divide_reg_init";
                  type = "integer";
                  default_value = "0x00000000";
                  editable = "1";
                  tooltip = "";
                }
                HDL_PARAMETER duty_cycle_reg_init
                {
                  parameter_name = "duty_cycle_reg_init";
                  type = "integer";
                  default_value = "0x00000000";
                  editable = "1";
                  tooltip = "";
                }
              }
            }
          }
        }
      }
      FILE pwm_register_file.v
      {
        file_mod = "Thu Jan 13 17:00:10 CST 2005";
        quartus_map_start = "Thu Jun 01 23:29:52 CST 2006";
        quartus_map_finished = "Thu Jun 01 23:29:59 CST 2006";
        #found 1 valid modules
        WRAPPER pwm_register_file
        {
          CLASS pwm_register_file
          {
            MODULE_DEFAULTS 
            {
              class = "pwm_register_file";
              class_version = "1.0";
              SYSTEM_BUILDER_INFO 
              {
                Instantiate_In_System_Module = "1";
              }
              SLAVE avalon_slave_0
              {
                SYSTEM_BUILDER_INFO 
                {
                  Bus_Type = "avalon";
                }
                PORT_WIRING 
                {
                  PORT clk
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "clk";
                    is_shared = "0";
                  }
                  PORT resetn
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT chip_select
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT address
                  {
                    width = "2";
                    width_expression = "";
                    direction = "input";
                    type = "address";
                    is_shared = "0";
                  }
                  PORT write
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "write";
                    is_shared = "0";
                  }
                  PORT write_data
                  {
                    width = "32";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT read
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "read";
                    is_shared = "0";
                  }
                  PORT read_data
                  {
                    width = "32";
                    width_expression = "";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT pwm_clock_divide
                  {
                    width = "32";
                    width_expression = "";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT pwm_duty_cycle
                  {
                    width = "32";
                    width_expression = "";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT pwm_enable
                  {
                    width = "1";
                    width_expression = "";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                }
              }
            }
            USER_INTERFACE 
            {
              USER_LABELS 
              {
                name = "pwm_register_file";
                technology = "imported components";
              }
            }
            CB_GENERATOR 
            {
              top_module_name = "pwm_register_file";
              emit_system_h = "0";
              HDL_FILES 
              {
                FILE 
                {
                  filepath = "D:/QProj/CC/pwm_source/pwm_hw/pwm_register_file.v";
                  use_in_simulation = "1";
                  use_in_synthesis = "1";
                }
              }
            }
            SOPC_Builder_Version = "0.0";
            COMPONENT_BUILDER 
            {
              HDL_PARAMETERS 
              {
                # generated by cbDocument.CBDocument.getParameterContainer:385
                # used only by Component Editor
                HDL_PARAMETER clock_divide_reg_init
                {
                  parameter_name = "clock_divide_reg_init";
                  type = "integer";
                  default_value = "0x00000000";
                  editable = "1";
                  tooltip = "";
                }
                HDL_PARAMETER duty_cycle_reg_init
                {
                  parameter_name = "duty_cycle_reg_init";
                  type = "integer";
                  default_value = "0x00000000";
                  editable = "1";
                  tooltip = "";
                }
              }
            }
          }
        }
      }
      FILE pwm_task_logic.v
      {
        file_mod = "Thu Jan 13 15:56:56 CST 2005";
        quartus_map_start = "Thu Jun 01 23:29:59 CST 2006";
        quartus_map_finished = "Thu Jun 01 23:30:04 CST 2006";
        #found 1 valid modules
        WRAPPER pwm_task_logic
        {
          CLASS pwm_task_logic
          {
            MODULE_DEFAULTS 
            {
              class = "pwm_task_logic";
              class_version = "1.0";
              SYSTEM_BUILDER_INFO 
              {
                Instantiate_In_System_Module = "1";
              }
              SLAVE avalon_slave_0
              {
                SYSTEM_BUILDER_INFO 
                {
                  Bus_Type = "avalon";
                }
                PORT_WIRING 
                {
                  PORT clk
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "clk";
                    is_shared = "0";
                  }
                  PORT clock_divide
                  {
                    width = "32";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT duty_cycle
                  {
                    width = "32";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT pwm_enable
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT resetn
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT pwm_out
                  {
                    width = "1";
                    width_expression = "";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                }
              }
            }
            USER_INTERFACE 
            {
              USER_LABELS 
              {
                name = "pwm_task_logic";
                technology = "imported components";
              }
            }
            CB_GENERATOR 
            {
              top_module_name = "pwm_task_logic";
              emit_system_h = "0";
              HDL_FILES 
              {
                FILE 
                {
                  filepath = "D:/QProj/CC/pwm_source/pwm_hw/pwm_task_logic.v";
                  use_in_simulation = "1";
                  use_in_synthesis = "1";
                }
              }
            }
            SOPC_Builder_Version = "0.0";
          }
        }
      }
    }
    HDL_PARAMETERS 
    {
      # generated by cbDocument.CBDocument.getParameterContainer:385
      # used only by Component Editor
      HDL_PARAMETER clock_divide_reg_init
      {
        parameter_name = "clock_divide_reg_init";
        type = "integer";
        default_value = "0x00000000";
        editable = "1";
        tooltip = "Initial PWM Period After Reset";
      }
      HDL_PARAMETER duty_cycle_reg_init
      {
        parameter_name = "duty_cycle_reg_init";
        type = "integer";
        default_value = "0x00000000";
        editable = "1";
        tooltip = "Initial Duty cycle After Reset";
      }
    }
    SW_FILES 
    {
      FILE 
      {
        filepath = "inc/altera_avalon_pwm_regs.h";
        type = "Registers (inc/)";
      }
      FILE 
      {
        filepath = "HAL/inc/altera_avalon_pwm_routines.h";
        type = "HAL (HAL/inc/)";
      }
      FILE 
      {
        filepath = "HAL/src/altera_avalon_pwm_routines.c";
        type = "HAL (HAL/src/)";
      }
    }
    built_on = "2006.06.01.23:42:54";
  }
  ASSOCIATED_FILES 
  {
    Add_Program = "the_wizard_ui";
    Edit_Program = "the_wizard_ui";
    Generator_Program = "cb_generator.pl";
  }
}