class.ptf

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

#
# This class.ptf file built by Component Editor
# 2006.06.01.23:42:54
#
# DO NOT MODIFY THIS FILE
# If you hand-modify this file you will likely
# interfere with Component Editor's ability to
# read and edit it. And then Component Editor
# will overwrite your changes anyway. So, for
# the very best results, just relax and
# DO NOT MODIFY THIS FILE
#
CLASS pwm_avalon_interface
{
  MODULE_DEFAULTS 
  {
    class = "pwm_avalon_interface";
    class_version = "1.0";
    SYSTEM_BUILDER_INFO 
    {
      Instantiate_In_System_Module = "1";
      Top_Level_Ports_Are_Enumerated = "1";
    }
    COMPONENT_BUILDER 
    {
      GLS_SETTINGS 
      {
      }
    }
    PORT_WIRING 
    {
    }
    SIMULATION 
    {
      DISPLAY 
      {
        SIGNAL x101
        {
          name = "pwm_avalon_interface/global_signals";
          format = "Divider";
        }
        SIGNAL x102
        {
          name = "pwm_avalon_interface/control_slave";
          format = "Divider";
        }
        SIGNAL x103
        {
          name = "clk";
        }
        SIGNAL x104
        {
          name = "resetn";
        }
        SIGNAL x105
        {
          name = "avalon_chip_select";
        }
        SIGNAL x106
        {
          name = "address";
          radix = "hexadecimal";
        }
        SIGNAL x107
        {
          name = "write";
        }
        SIGNAL x108
        {
          name = "write_data";
          radix = "hexadecimal";
        }
        SIGNAL x109
        {
          name = "read";
        }
        SIGNAL x110
        {
          name = "read_data";
          radix = "hexadecimal";
        }
        SIGNAL x111
        {
          name = "pwm_out";
        }
      }
    }
    WIZARD_SCRIPT_ARGUMENTS 
    {
      hdl_parameters 
      {
        clock_divide_reg_init = "0x00000000";
        duty_cycle_reg_init = "0x00000000";
      }
    }
    SLAVE control_slave
    {
      SYSTEM_BUILDER_INFO 
      {
        Bus_Type = "avalon";
        Address_Width = "2";
        Address_Alignment = "native";
        Data_Width = "32";
        Has_Base_Address = "1";
        Has_IRQ = "0";
        Setup_Time = "0cycles";
        Hold_Time = "0cycles";
        Read_Wait_States = "0cycles";
        Write_Wait_States = "0cycles";
        Read_Latency = "0";
        Maximum_Pending_Read_Transactions = "0";
        Is_Printable_Device = "0";
        Is_Memory_Device = "0";
        Is_Readable = "1";
        Is_Writable = "1";
        Minimum_Uninterrupted_Run_Length = "1";
      }
      COMPONENT_BUILDER 
      {
        AVS_SETTINGS 
        {
          Setup_Value = "0";
          Read_Wait_Value = "0";
          Write_Wait_Value = "0";
          Hold_Value = "0";
          Timing_Units = "cycles";
          Read_Latency_Value = "0";
          Max_Pending_Read_Transactions_Value = "1";
          Address_Alignment = "native";
          Is_Printable_Device = "0";
          interface_name = "Avalon Slave";
          Minimum_Arbitration_Shares = "1";
          external_wait = "0";
          Is_Memory_Device = "0";
        }
      }
      PORT_WIRING 
      {
        PORT clk
        {
          width = "1";
          width_expression = "";
          direction = "input";
          type = "clk";
          is_shared = "0";
        }
        PORT resetn
        {
          width = "1";
          width_expression = "";
          direction = "input";
          type = "reset_n";
          is_shared = "0";
        }
        PORT avalon_chip_select
        {
          width = "1";
          width_expression = "";
          direction = "input";
          type = "chipselect";
          is_shared = "0";
        }
        PORT address
        {
          width = "2";
          width_expression = "";
          direction = "input";
          type = "address";
          is_shared = "0";
        }
        PORT write
        {
          width = "1";
          width_expression = "";
          direction = "input";
          type = "write";
          is_shared = "0";
        }
        PORT write_data
        {
          width = "32";
          width_expression = "";
          direction = "input";
          type = "writedata";
          is_shared = "0";
        }
        PORT read
        {
          width = "1";
          width_expression = "";
          direction = "input";
          type = "read";
          is_shared = "0";
        }
        PORT read_data
        {
          width = "32";
          width_expression = "";
          direction = "output";
          type = "readdata";
          is_shared = "0";
        }
        PORT pwm_out
        {
          width = "1";
          width_expression = "";
          direction = "output";
          type = "export";
          is_shared = "0";
        }
      }
    }
  }
  USER_INTERFACE 
  {
    USER_LABELS 
    {
      name = "pwm_avalon_interface";
      technology = "User Logic";
    }
    WIZARD_UI the_wizard_ui
    {
      title = "pwm_avalon_interface - {{ $MOD }}";
      CONTEXT 
      {
        H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
        M = "";
        SBI_ = "SYSTEM_BUILDER_INFO";
        SBI_control_slave = "SLAVE control_slave/SYSTEM_BUILDER_INFO";
      }
      PAGES main
      {
        PAGE 1
        {
          align = "left";
          title = "<b>pwm_avalon_interface 1.0</b> Settings";
          layout = "vertical";
          TEXT 
          {
            title = "Built on: 2006.06.01.23:42:54";
          }
          TEXT 
          {
            title = "Class name: pwm_avalon_interface";
          }
          TEXT 
          {
            title = "Class version: 1.0";
          }
          TEXT 
          {
            title = "Component name: pwm_avalon_interface";
          }
          TEXT 
          {
            title = "Component Group: User Logic";
          }
          GROUP parameters
          {
            title = "Parameters";
            layout = "form";
            align = "left";
            EDIT e1
            {
              editable = "1";
              title = "clock_divide_reg_init:";
              columns = "40";
              tooltip = "Initial PWM Period After Reset";
              DATA 
              {
                $H/clock_divide_reg_init = "$";
              }
              q = "'";
              warning = "{{ if(!(regexp('ugly_'+$H/clock_divide_reg_init,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/clock_divide_reg_init,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/clock_divide_reg_init,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/clock_divide_reg_init,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/clock_divide_reg_init,'ugly_-?[0-9]+')))'clock_divide_reg_init must be numeric constant, not '+$H/clock_divide_reg_init; }}";
            }
            EDIT e2
            {
              editable = "1";
              title = "duty_cycle_reg_init:";
              columns = "40";
              tooltip = "Initial Duty cycle After Reset";
              DATA 
              {
                $H/duty_cycle_reg_init = "$";
              }
              q = "'";
              warning = "{{ if(!(regexp('ugly_'+$H/duty_cycle_reg_init,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/duty_cycle_reg_init,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/duty_cycle_reg_init,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/duty_cycle_reg_init,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/duty_cycle_reg_init,'ugly_-?[0-9]+')))'duty_cycle_reg_init must be numeric constant, not '+$H/duty_cycle_reg_init; }}";
            }
          }
        }
      }
    }
  }
  CB_GENERATOR 
  {
    top_module_name = "pwm_avalon_interface.v:pwm_avalon_interface";
    emit_system_h = "0";
    HDL_FILES 
    {
      FILE 
      {
        filepath = "hdl/pwm_avalon_interface.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/pwm_register_file.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/pwm_task_logic.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
    }
  }
  SOPC_Builder_Version = "5.00";
  COMPONENT_BUILDER 
  {
    CACHED_HDL_INFO 
    {
      # cached hdl info, emitted by cbGuinevereApp.CBFrameRealtime.getDocumentCachedHDLInfoSection:123
      # used only by Component Builder
      FILE pwm_avalon_interface.v
      {
        file_mod = "Fri Jan 14 17:55:44 CST 2005";
        quartus_map_start = "Thu Jun 01 23:29:19 CST 2006";
        quartus_map_finished = "Thu Jun 01 23:29:50 CST 2006";
        #found 1 valid modules
        WRAPPER pwm_avalon_interface
        {
          CLASS pwm_avalon_interface
          {
            MODULE_DEFAULTS 
            {
              class = "pwm_avalon_interface";
              class_version = "1.0";
              SYSTEM_BUILDER_INFO 
              {
                Instantiate_In_System_Module = "1";
              }
              SLAVE avalon_slave_0
              {
                SYSTEM_BUILDER_INFO 
                {
                  Bus_Type = "avalon";
                }
                PORT_WIRING 
                {
                  PORT clk
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "clk";
                    is_shared = "0";
                  }
                  PORT resetn
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT avalon_chip_select
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT address
                  {
                    width = "2";
                    width_expression = "";
                    direction = "input";
                    type = "address";
                    is_shared = "0";
                  }
                  PORT write
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "write";
                    is_shared = "0";
                  }
                  PORT write_data
                  {
                    width = "32";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";