test_led.map.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "module_input15 CPU_jtag_debug_module_wrapper.vhd(180) " "Info: (10035) Verilog HDL or VHDL information at CPU_jtag_debug_module_wrapper.vhd(180): object \"module_input15\" declared but not used" {  } { { "CPU_jtag_debug_module_wrapper.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module_wrapper.vhd" 180 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "module_input16 CPU_jtag_debug_module_wrapper.vhd(181) " "Info: (10035) Verilog HDL or VHDL information at CPU_jtag_debug_module_wrapper.vhd(181): object \"module_input16\" declared but not used" {  } { { "CPU_jtag_debug_module_wrapper.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module_wrapper.vhd" 181 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "module_input17 CPU_jtag_debug_module_wrapper.vhd(182) " "Info: (10035) Verilog HDL or VHDL information at CPU_jtag_debug_module_wrapper.vhd(182): object \"module_input17\" declared but not used" {  } { { "CPU_jtag_debug_module_wrapper.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module_wrapper.vhd" 182 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "module_input18 CPU_jtag_debug_module_wrapper.vhd(183) " "Info: (10035) Verilog HDL or VHDL information at CPU_jtag_debug_module_wrapper.vhd(183): object \"module_input18\" declared but not used" {  } { { "CPU_jtag_debug_module_wrapper.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module_wrapper.vhd" 183 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "module_input19 CPU_jtag_debug_module_wrapper.vhd(184) " "Info: (10035) Verilog HDL or VHDL information at CPU_jtag_debug_module_wrapper.vhd(184): object \"module_input19\" declared but not used" {  } { { "CPU_jtag_debug_module_wrapper.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module_wrapper.vhd" 184 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "module_input20 CPU_jtag_debug_module_wrapper.vhd(185) " "Info: (10035) Verilog HDL or VHDL information at CPU_jtag_debug_module_wrapper.vhd(185): object \"module_input20\" declared but not used" {  } { { "CPU_jtag_debug_module_wrapper.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module_wrapper.vhd" 185 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "CPU_jtag_debug_module.vhd 2 1 " "Info: Using design file CPU_jtag_debug_module.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CPU_jtag_debug_module-europa " "Info: Found design unit 1: CPU_jtag_debug_module-europa" {  } { { "CPU_jtag_debug_module.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module.vhd" 69 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 CPU_jtag_debug_module " "Info: Found entity 1: CPU_jtag_debug_module" {  } { { "CPU_jtag_debug_module.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module.vhd" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CPU_jtag_debug_module first_nios2_system:inst\|CPU:the_CPU\|CPU_nios2_oci:the_CPU_nios2_oci\|CPU_jtag_debug_module_wrapper:the_CPU_jtag_debug_module_wrapper\|CPU_jtag_debug_module:the_CPU_jtag_debug_module1 " "Info: Elaborating entity \"CPU_jtag_debug_module\" for hierarchy \"first_nios2_system:inst\|CPU:the_CPU\|CPU_nios2_oci:the_CPU_nios2_oci\|CPU_jtag_debug_module_wrapper:the_CPU_jtag_debug_module_wrapper\|CPU_jtag_debug_module:the_CPU_jtag_debug_module1\"" {  } { { "CPU_jtag_debug_module_wrapper.vhd" "the_CPU_jtag_debug_module1" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module_wrapper.vhd" 284 -1 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "CPU_jtag_debug_module.vhd(142) " "Info: VHDL Case Statement information at CPU_jtag_debug_module.vhd(142): OTHERS choice is never selected" {  } { { "CPU_jtag_debug_module.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module.vhd" 142 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "CPU_jtag_debug_module.vhd(180) " "Info: VHDL Case Statement information at CPU_jtag_debug_module.vhd(180): OTHERS choice is never selected" {  } { { "CPU_jtag_debug_module.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module.vhd" 180 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "usr1 CPU_jtag_debug_module.vhd(236) " "Warning: VHDL Process Statement warning at CPU_jtag_debug_module.vhd(236): signal \"usr1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CPU_jtag_debug_module.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module.vhd" 236 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ena CPU_jtag_debug_module.vhd(236) " "Warning: VHDL Process Statement warning at CPU_jtag_debug_module.vhd(236): signal \"ena\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CPU_jtag_debug_module.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module.vhd" 236 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "usr1 CPU_jtag_debug_module.vhd(239) " "Warning: VHDL Process Statement warning at CPU_jtag_debug_module.vhd(239): signal \"usr1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CPU_jtag_debug_module.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module.vhd" 239 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ena CPU_jtag_debug_module.vhd(239) " "Warning: VHDL Process Statement warning at CPU_jtag_debug_module.vhd(239): signal \"ena\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CPU_jtag_debug_module.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module.vhd" 239 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "irq CPU_jtag_debug_module.vhd(47) " "Warning: Output port \"irq\" at CPU_jtag_debug_module.vhd(47) has no driver" {  } { { "CPU_jtag_debug_module.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module.vhd" 47 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LED_PIO_s1_arbitrator first_nios2_system:inst\|LED_PIO_s1_arbitrator:the_LED_PIO_s1 " "Info: Elaborating entity \"LED_PIO_s1_arbitrator\" for hierarchy \"first_nios2_system:inst\|LED_PIO_s1_arbitrator:the_LED_PIO_s1\"" {  } { { "first_nios2_system.vhd" "the_LED_PIO_s1" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 2468 -1 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "CPU_data_master_read_data_valid_LED_PIO_s1 first_nios2_system.vhd(685) " "Warning: Output port \"CPU_data_master_read_data_valid_LED_PIO_s1\" at first_nios2_system.vhd(685) has no driver" {  } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 685 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "LED_PIO.vhd 2 1 " "Info: Using design file LED_PIO.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LED_PIO-europa " "Info: Found design unit 1: LED_PIO-europa" {  } { { "LED_PIO.vhd" "" { Text "E:/QProj/Test_LED/LED_PIO.vhd" 37 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 LED_PIO " "Info: Found entity 1: LED_PIO" {  } { { "LED_PIO.vhd" "" { Text "E:/QProj/Test_LED/LED_PIO.vhd" 21 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LED_PIO first_nios2_system:inst\|LED_PIO:the_LED_PIO " "Info: Elaborating entity \"LED_PIO\" for hierarchy \"first_nios2_system:inst\|LED_PIO:the_LED_PIO\"" {  } { { "first_nios2_system.vhd" "the_LED_PIO" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 2491 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "onchip_RAM_s1_arbitrator first_nios2_system:inst\|onchip_RAM_s1_arbitrator:the_onchip_RAM_s1 " "Info: Elaborating entity \"onchip_RAM_s1_arbitrator\" for hierarchy \"first_nios2_system:inst\|onchip_RAM_s1_arbitrator:the_onchip_RAM_s1\"" {  } { { "first_nios2_system.vhd" "the_onchip_RAM_s1" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 2504 -1 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "onchip_RAM.vhd 2 1 " "Info: Using design file onchip_RAM.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 onchip_RAM-europa " "Info: Found design unit 1: onchip_RAM-europa" {  } { { "onchip_RAM.vhd" "" { Text "E:/QProj/Test_LED/onchip_RAM.vhd" 44 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 onchip_RAM " "Info: Found entity 1: onchip_RAM" {  } { { "onchip_RAM.vhd" "" { Text "E:/QProj/Test_LED/onchip_RAM.vhd" 27 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "onchip_RAM first_nios2_system:inst\|onchip_RAM:the_onchip_RAM " "Info: Elaborating entity \"onchip_RAM\" for hierarchy \"first_nios2_system:inst\|onchip_RAM:the_onchip_RAM\"" {  } { { "first_nios2_system.vhd" "the_onchip_RAM" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 2539 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram first_nios2_system:inst\|onchip_RAM:the_onchip_RAM\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"first_nios2_system:inst\|onchip_RAM:the_onchip_RAM\|altsyncram:the_altsyncram\"" {  } { { "onchip_RAM.vhd" "the_altsyncram" { Text "E:/QProj/Test_LED/onchip_RAM.vhd" 134 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_1a01.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_1a01.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_1a01 " "Info: Found entity 1: altsyncram_1a01" {  } { { "db/altsyncram_1a01.tdf" "" { Text "E:/QProj/Test_LED/db/altsyncram_1a01.tdf