test_led.map.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_15_is_x CPU_test_bench.vhd(71) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(71): object \"M_wr_data_unfiltered_15_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 71 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_16_is_x CPU_test_bench.vhd(72) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(72): object \"M_wr_data_unfiltered_16_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 72 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_17_is_x CPU_test_bench.vhd(73) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(73): object \"M_wr_data_unfiltered_17_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 73 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_18_is_x CPU_test_bench.vhd(74) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(74): object \"M_wr_data_unfiltered_18_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 74 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_19_is_x CPU_test_bench.vhd(75) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(75): object \"M_wr_data_unfiltered_19_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 75 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_1_is_x CPU_test_bench.vhd(76) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(76): object \"M_wr_data_unfiltered_1_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 76 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_20_is_x CPU_test_bench.vhd(77) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(77): object \"M_wr_data_unfiltered_20_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 77 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_21_is_x CPU_test_bench.vhd(78) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(78): object \"M_wr_data_unfiltered_21_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 78 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_22_is_x CPU_test_bench.vhd(79) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(79): object \"M_wr_data_unfiltered_22_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 79 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_23_is_x CPU_test_bench.vhd(80) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(80): object \"M_wr_data_unfiltered_23_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 80 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_24_is_x CPU_test_bench.vhd(81) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(81): object \"M_wr_data_unfiltered_24_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 81 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_25_is_x CPU_test_bench.vhd(82) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(82): object \"M_wr_data_unfiltered_25_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 82 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_26_is_x CPU_test_bench.vhd(83) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(83): object \"M_wr_data_unfiltered_26_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 83 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_27_is_x CPU_test_bench.vhd(84) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(84): object \"M_wr_data_unfiltered_27_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 84 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_28_is_x CPU_test_bench.vhd(85) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(85): object \"M_wr_data_unfiltered_28_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 85 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_29_is_x CPU_test_bench.vhd(86) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(86): object \"M_wr_data_unfiltered_29_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 86 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_2_is_x CPU_test_bench.vhd(87) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(87): object \"M_wr_data_unfiltered_2_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 87 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_30_is_x CPU_test_bench.vhd(88) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(88): object \"M_wr_data_unfiltered_30_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 88 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_31_is_x CPU_test_bench.vhd(89) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(89): object \"M_wr_data_unfiltered_31_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 89 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_3_is_x CPU_test_bench.vhd(90) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(90): object \"M_wr_data_unfiltered_3_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 90 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_4_is_x CPU_test_bench.vhd(91) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(91): object \"M_wr_data_unfiltered_4_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 91 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_5_is_x CPU_test_bench.vhd(92) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(92): object \"M_wr_data_unfiltered_5_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 92 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_6_is_x CPU_test_bench.vhd(93) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(93): object \"M_wr_data_unfiltered_6_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 93 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_7_is_x CPU_test_bench.vhd(94) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(94): object \"M_wr_data_unfiltered_7_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 94 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_8_is_x CPU_test_bench.vhd(95) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(95): object \"M_wr_data_unfiltered_8_is_x\" declared but not used" {  } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 95 0 0 } }  } 0}