📄 test_led.map.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 10:06:06 2006 " "Info: Processing started: Fri Apr 14 10:06:06 2006" { } { } 0} } { } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Test_LED -c Test_LED " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Test_LED -c Test_LED" { } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Test_LED.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Test_LED.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Test_LED " "Info: Found entity 1: Test_LED" { } { { "Test_LED.bdf" "" { Schematic "E:/QProj/Test_LED/Test_LED.bdf" { } } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altera_vhdl_support.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file altera_vhdl_support.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 altera_vhdl_support_lib " "Info: Found design unit 1: altera_vhdl_support_lib" { } { { "altera_vhdl_support.vhd" "" { Text "E:/QProj/Test_LED/altera_vhdl_support.vhd" 14 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 altera_vhdl_support_lib-body " "Info: Found design unit 2: altera_vhdl_support_lib-body" { } { { "altera_vhdl_support.vhd" "" { Text "E:/QProj/Test_LED/altera_vhdl_support.vhd" 110 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Test_LED " "Info: Elaborating entity \"Test_LED\" for the top level hierarchy" { } { } 0}
{ "Info" "ISGN_SEARCH_FILE" "first_nios2_system.vhd 18 9 " "Info: Using design file first_nios2_system.vhd, which is not specified as a design file for the current project, but contains definitions for 18 design units and 9 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CPU_jtag_debug_module_arbitrator-europa " "Info: Found design unit 1: CPU_jtag_debug_module_arbitrator-europa" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 73 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 CPU_data_master_arbitrator-europa " "Info: Found design unit 2: CPU_data_master_arbitrator-europa" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 424 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 CPU_instruction_master_arbitrator-europa " "Info: Found design unit 3: CPU_instruction_master_arbitrator-europa" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 516 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 LED_PIO_s1_arbitrator-europa " "Info: Found design unit 4: LED_PIO_s1_arbitrator-europa" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 699 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 onchip_RAM_s1_arbitrator-europa " "Info: Found design unit 5: onchip_RAM_s1_arbitrator-europa" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 901 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 onchip_ROM_s1_arbitrator-europa " "Info: Found design unit 6: onchip_ROM_s1_arbitrator-europa" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 1280 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 sysid_control_slave_arbitrator-europa " "Info: Found design unit 7: sysid_control_slave_arbitrator-europa" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 1640 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "8 first_nios2_system_reset_clk_domain_synch_module-europa " "Info: Found design unit 8: first_nios2_system_reset_clk_domain_synch_module-europa" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 1807 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "9 first_nios2_system-europa " "Info: Found design unit 9: first_nios2_system-europa" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 1863 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "1 CPU_jtag_debug_module_arbitrator " "Info: Found entity 1: CPU_jtag_debug_module_arbitrator" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 29 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "2 CPU_data_master_arbitrator " "Info: Found entity 2: CPU_data_master_arbitrator" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 373 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "3 CPU_instruction_master_arbitrator " "Info: Found entity 3: CPU_instruction_master_arbitrator" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 478 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "4 LED_PIO_s1_arbitrator " "Info: Found entity 4: LED_PIO_s1_arbitrator" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 671 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "5 onchip_RAM_s1_arbitrator " "Info: Found entity 5: onchip_RAM_s1_arbitrator" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 861 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "6 onchip_ROM_s1_arbitrator " "Info: Found entity 6: onchip_ROM_s1_arbitrator" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 1238 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "7 sysid_control_slave_arbitrator " "Info: Found entity 7: sysid_control_slave_arbitrator" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 1616 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "8 first_nios2_system_reset_clk_domain_synch_module " "Info: Found entity 8: first_nios2_system_reset_clk_domain_synch_module" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 1794 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "9 first_nios2_system " "Info: Found entity 9: first_nios2_system" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 1851 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "first_nios2_system first_nios2_system:inst " "Info: Elaborating entity \"first_nios2_system\" for hierarchy \"first_nios2_system:inst\"" { } { { "Test_LED.bdf" "inst" { Schematic "E:/QProj/Test_LED/Test_LED.bdf" { { 64 160 408 176 "inst" "" } } } } } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CPU_jtag_debug_module_arbitrator first_nios2_system:inst\|CPU_jtag_debug_module_arbitrator:the_CPU_jtag_debug_module " "Info: Elaborating entity \"CPU_jtag_debug_module_arbitrator\" for hierarchy \"first_nios2_system:inst\|CPU_jtag_debug_module_arbitrator:the_CPU_jtag_debug_module\"" { } { { "first_nios2_system.vhd" "the_CPU_jtag_debug_module" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 2317 -1 0 } } } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "CPU_data_master_read_data_valid_CPU_jtag_debug_module first_nios2_system.vhd(49) " "Warning: Output port \"CPU_data_master_read_data_valid_CPU_jtag_debug_module\" at first_nios2_system.vhd(49) has no driver" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 49 0 0 } } } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CPU_data_master_arbitrator first_nios2_system:inst\|CPU_data_master_arbitrator:the_CPU_data_master " "Info: Elaborating entity \"CPU_data_master_arbitrator\" for hierarchy \"first_nios2_system:inst\|CPU_data_master_arbitrator:the_CPU_data_master\"" { } { { "first_nios2_system.vhd" "the_CPU_data_master" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 2356 -1 0 } } } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CPU_instruction_master_arbitrator first_nios2_system:inst\|CPU_instruction_master_arbitrator:the_CPU_instruction_master " "Info: Elaborating entity \"CPU_instruction_master_arbitrator\" for hierarchy \"first_nios2_system:inst\|CPU_instruction_master_arbitrator:the_CPU_instruction_master\"" { } { { "first_nios2_system.vhd" "the_CPU_instruction_master" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 2402 -1 0 } } } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "CPU_instruction_master_address_last_time first_nios2_system.vhd(517) " "Info: (10035) Verilog HDL or VHDL information at first_nios2_system.vhd(517): object \"CPU_instruction_master_address_last_time\" declared but not used" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 517 0 0 } } } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "CPU_instruction_master_read_last_time first_nios2_system.vhd(520) " "Info: (10035) Verilog HDL or VHDL information at first_nios2_system.vhd(520): object \"CPU_instruction_master_read_last_time\" declared but not used" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 520 0 0 } } } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "active_and_waiting_last_time first_nios2_system.vhd(522) " "Info: (10035) Verilog HDL or VHDL information at first_nios2_system.vhd(522): object \"active_and_waiting_last_time\" declared but not used" { } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 522 0 0 } } } 0}
{ "Info" "ISGN_SEARCH_FILE" "CPU.vhd 52 26 " "Info: Using design file CPU.vhd, which is not specified as a design file for the current project, but contains definitions for 52 design units and 26 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CPU_ic_data_module-europa " "Info: Found design unit 1: CPU_ic_data_module-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 47 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 CPU_ic_tag_module-europa " "Info: Found design unit 2: CPU_ic_tag_module-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 209 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 CPU_register_bank_a_module-europa " "Info: Found design unit 3: CPU_register_bank_a_module-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 375 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 CPU_register_bank_b_module-europa " "Info: Found design unit 4: CPU_register_bank_b_module-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 541 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 CPU_nios2_oci_debug-europa " "Info: Found design unit 5: CPU_nios2_oci_debug-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 710 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 CPU_ociram_lpm_dram_bdp_component_module-europa " "Info: Found design unit 6: CPU_ociram_lpm_dram_bdp_component_module-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 815 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 CPU_nios2_ocimem-europa " "Info: Found design unit 7: CPU_nios2_ocimem-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 948 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "8 CPU_nios2_avalon_reg-europa " "Info: Found design unit 8: CPU_nios2_avalon_reg-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 1102 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "9 CPU_nios2_oci_break-europa " "Info: Found design unit 9: CPU_nios2_oci_break-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 1213 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "10 CPU_nios2_oci_xbrk-europa " "Info: Found design unit 10: CPU_nios2_oci_xbrk-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 1661 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "11 CPU_nios2_oci_match_paired-europa " "Info: Found design unit 11: CPU_nios2_oci_match_paired-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 1853 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "12 CPU_nios2_oci_match_single-europa " "Info: Found design unit 12: CPU_nios2_oci_match_single-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 1887 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "13 CPU_nios2_oci_dbrk-europa " "Info: Found design unit 13: CPU_nios2_oci_dbrk-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 1948 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "14 CPU_nios2_oci_itrace-europa " "Info: Found design unit 14: CPU_nios2_oci_itrace-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 2196 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "15 CPU_nios2_oci_td_mode-europa " "Info: Found design unit 15: CPU_nios2_oci_td_mode-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 2393 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "16 CPU_nios2_oci_dtrace-europa " "Info: Found design unit 16: CPU_nios2_oci_dtrace-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 2473 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "17 CPU_nios2_oci_compute_tm_count-europa " "Info: Found design unit 17: CPU_nios2_oci_compute_tm_count-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 2563 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "18 CPU_nios2_oci_fifowp_inc-europa " "Info: Found design unit 18: CPU_nios2_oci_fifowp_inc-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 2636 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "19 CPU_nios2_oci_fifocount_inc-europa " "Info: Found design unit 19: CPU_nios2_oci_fifocount_inc-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 2680 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "20 CPU_nios2_oci_fifo-europa " "Info: Found design unit 20: CPU_nios2_oci_fifo-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 2732 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "21 CPU_nios2_oci_pib-europa " "Info: Found design unit 21: CPU_nios2_oci_pib-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 3167 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "22 CPU_traceram_lpm_dram_bdp_component_module-europa " "Info: Found design unit 22: CPU_traceram_lpm_dram_bdp_component_module-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 3245 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "23 CPU_nios2_oci_im-europa " "Info: Found design unit 23: CPU_nios2_oci_im-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 3375 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "24 CPU_nios2_performance_monitors-europa " "Info: Found design unit 24: CPU_nios2_performance_monitors-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 3509 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "25 CPU_nios2_oci-europa " "Info: Found design unit 25: CPU_nios2_oci-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 3578 -1 0 } } } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "26 CPU-europa " "Info: Found design unit 26: CPU-europa" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 4431 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "1 CPU_ic_data_module " "Info: Found entity 1: CPU_ic_data_module" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 27 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "2 CPU_ic_tag_module " "Info: Found entity 2: CPU_ic_tag_module" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 189 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "3 CPU_register_bank_a_module " "Info: Found entity 3: CPU_register_bank_a_module" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 355 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "4 CPU_register_bank_b_module " "Info: Found entity 4: CPU_register_bank_b_module" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 521 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "5 CPU_nios2_oci_debug " "Info: Found entity 5: CPU_nios2_oci_debug" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 681 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "6 CPU_ociram_lpm_dram_bdp_component_module " "Info: Found entity 6: CPU_ociram_lpm_dram_bdp_component_module" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 790 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "7 CPU_nios2_ocimem " "Info: Found entity 7: CPU_nios2_ocimem" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 923 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "8 CPU_nios2_avalon_reg " "Info: Found entity 8: CPU_nios2_avalon_reg" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 1077 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "9 CPU_nios2_oci_break " "Info: Found entity 9: CPU_nios2_oci_break" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 1165 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "10 CPU_nios2_oci_xbrk " "Info: Found entity 10: CPU_nios2_oci_xbrk" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 1630 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "11 CPU_nios2_oci_match_paired " "Info: Found entity 11: CPU_nios2_oci_match_paired" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 1837 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "12 CPU_nios2_oci_match_single " "Info: Found entity 12: CPU_nios2_oci_match_single" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 1872 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "13 CPU_nios2_oci_dbrk " "Info: Found entity 13: CPU_nios2_oci_dbrk" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 1906 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "14 CPU_nios2_oci_itrace " "Info: Found entity 14: CPU_nios2_oci_itrace" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 2153 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "15 CPU_nios2_oci_td_mode " "Info: Found entity 15: CPU_nios2_oci_td_mode" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 2382 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "16 CPU_nios2_oci_dtrace " "Info: Found entity 16: CPU_nios2_oci_dtrace" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 2453 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "17 CPU_nios2_oci_compute_tm_count " "Info: Found entity 17: CPU_nios2_oci_compute_tm_count" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 2550 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "18 CPU_nios2_oci_fifowp_inc " "Info: Found entity 18: CPU_nios2_oci_fifowp_inc" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 2623 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "19 CPU_nios2_oci_fifocount_inc " "Info: Found entity 19: CPU_nios2_oci_fifocount_inc" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 2666 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "20 CPU_nios2_oci_fifo " "Info: Found entity 20: CPU_nios2_oci_fifo" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 2712 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "21 CPU_nios2_oci_pib " "Info: Found entity 21: CPU_nios2_oci_pib" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 3152 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "22 CPU_traceram_lpm_dram_bdp_component_module " "Info: Found entity 22: CPU_traceram_lpm_dram_bdp_component_module" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 3221 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "23 CPU_nios2_oci_im " "Info: Found entity 23: CPU_nios2_oci_im" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 3349 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "24 CPU_nios2_performance_monitors " "Info: Found entity 24: CPU_nios2_performance_monitors" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 3505 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "25 CPU_nios2_oci " "Info: Found entity 25: CPU_nios2_oci" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 3525 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "26 CPU " "Info: Found entity 26: CPU" { } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 4395 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CPU first_nios2_system:inst\|CPU:the_CPU " "Info: Elaborating entity \"CPU\" for hierarchy \"first_nios2_system:inst\|CPU:the_CPU\"" { } { { "first_nios2_system.vhd" "the_CPU" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 2435 -1 0 } } } 0}
{ "Info" "ISGN_SEARCH_FILE" "CPU_test_bench.vhd 2 1 " "Info: Using design file CPU_test_bench.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CPU_test_bench-europa " "Info: Found design unit 1: CPU_test_bench-europa" { } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 62 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "1 CPU_test_bench " "Info: Found entity 1: CPU_test_bench" { } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 12 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CPU_test_bench first_nios2_system:inst\|CPU:the_CPU\|CPU_test_bench:the_CPU_test_bench " "Info: Elaborating entity \"CPU_test_bench\" for hierarchy \"first_nios2_system:inst\|CPU:the_CPU\|CPU_test_bench:the_CPU_test_bench\"" { } { { "CPU.vhd" "the_CPU_test_bench" { Text "E:/QProj/Test_LED/CPU.vhd" 5719 -1 0 } } } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_0_is_x CPU_test_bench.vhd(65) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(65): object \"M_wr_data_unfiltered_0_is_x\" declared but not used" { } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 65 0 0 } } } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_10_is_x CPU_test_bench.vhd(66) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(66): object \"M_wr_data_unfiltered_10_is_x\" declared but not used" { } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 66 0 0 } } } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_11_is_x CPU_test_bench.vhd(67) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(67): object \"M_wr_data_unfiltered_11_is_x\" declared but not used" { } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 67 0 0 } } } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_12_is_x CPU_test_bench.vhd(68) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(68): object \"M_wr_data_unfiltered_12_is_x\" declared but not used" { } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 68 0 0 } } } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_13_is_x CPU_test_bench.vhd(69) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(69): object \"M_wr_data_unfiltered_13_is_x\" declared but not used" { } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 69 0 0 } } } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_14_is_x CPU_test_bench.vhd(70) " "Info: (10035) Verilog HDL or VHDL information at CPU_test_bench.vhd(70): object \"M_wr_data_unfiltered_14_is_x\" declared but not used" { } { { "CPU_test_bench.vhd" "" { Text "E:/QProj/Test_LED/CPU_test_bench.vhd" 70 0 0 } } } 0}
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