test_led.hif

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

ON
}
# case_insensitive
# source_file
CPU.vhd
1144980047
4
# storage
db|Test_LED.(33).cnf
db|Test_LED.(33).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
altera_vhdl_support.vhd
1144980097
}
# hierarchies {
first_nios2_system:inst|CPU:the_CPU|CPU_nios2_oci:the_CPU_nios2_oci|CPU_nios2_oci_dtrace:the_CPU_nios2_oci_dtrace|CPU_nios2_oci_td_mode:CPU_nios2_oci_trc_ctrl_td_mode
}
# end
# entity
CPU_nios2_oci_fifo
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
CPU.vhd
1144980047
4
# storage
db|Test_LED.(34).cnf
db|Test_LED.(34).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
altera_vhdl_support.vhd
1144980097
}
# hierarchies {
first_nios2_system:inst|CPU:the_CPU|CPU_nios2_oci:the_CPU_nios2_oci|CPU_nios2_oci_fifo:the_CPU_nios2_oci_fifo
}
# end
# entity
CPU_nios2_oci_compute_tm_count
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
CPU.vhd
1144980047
4
# storage
db|Test_LED.(35).cnf
db|Test_LED.(35).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
altera_vhdl_support.vhd
1144980097
}
# hierarchies {
first_nios2_system:inst|CPU:the_CPU|CPU_nios2_oci:the_CPU_nios2_oci|CPU_nios2_oci_fifo:the_CPU_nios2_oci_fifo|CPU_nios2_oci_compute_tm_count:CPU_nios2_oci_compute_tm_count_tm_count
}
# end
# entity
CPU_nios2_oci_fifowp_inc
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
CPU.vhd
1144980047
4
# storage
db|Test_LED.(36).cnf
db|Test_LED.(36).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
altera_vhdl_support.vhd
1144980097
}
# hierarchies {
first_nios2_system:inst|CPU:the_CPU|CPU_nios2_oci:the_CPU_nios2_oci|CPU_nios2_oci_fifo:the_CPU_nios2_oci_fifo|CPU_nios2_oci_fifowp_inc:CPU_nios2_oci_fifowp_inc_fifowp
}
# end
# entity
CPU_nios2_oci_fifocount_inc
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
CPU.vhd
1144980047
4
# storage
db|Test_LED.(37).cnf
db|Test_LED.(37).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
altera_vhdl_support.vhd
1144980097
}
# hierarchies {
first_nios2_system:inst|CPU:the_CPU|CPU_nios2_oci:the_CPU_nios2_oci|CPU_nios2_oci_fifo:the_CPU_nios2_oci_fifo|CPU_nios2_oci_fifocount_inc:CPU_nios2_oci_fifocount_inc_fifocount
}
# end
# entity
CPU_nios2_oci_pib
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
CPU.vhd
1144980047
4
# storage
db|Test_LED.(38).cnf
db|Test_LED.(38).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
altera_vhdl_support.vhd
1144980097
}
# hierarchies {
first_nios2_system:inst|CPU:the_CPU|CPU_nios2_oci:the_CPU_nios2_oci|CPU_nios2_oci_pib:the_CPU_nios2_oci_pib
}
# end
# entity
CPU_nios2_oci_im
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
CPU.vhd
1144980047
4
# storage
db|Test_LED.(39).cnf
db|Test_LED.(39).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
altera_vhdl_support.vhd
1144980097
}
# hierarchies {
first_nios2_system:inst|CPU:the_CPU|CPU_nios2_oci:the_CPU_nios2_oci|CPU_nios2_oci_im:the_CPU_nios2_oci_im
}
# end
# entity
CPU_traceram_lpm_dram_bdp_component_module
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
CPU.vhd
1144980047
4
# storage
db|Test_LED.(40).cnf
db|Test_LED.(40).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file

PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
1144980097
}
# hierarchies {
first_nios2_system:inst|CPU:the_CPU|CPU_nios2_oci:the_CPU_nios2_oci|CPU_nios2_oci_im:the_CPU_nios2_oci_im|CPU_traceram_lpm_dram_bdp_component_module:CPU_traceram_lpm_dram_bdp_component
}
# end
# entity
altsyncram
# case_insensitive
# source_file
d:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|Test_LED.(41).cnf
db|Test_LED.(41).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
36
PARAMETER_DEC
USR
WIDTHAD_A
7
PARAMETER_DEC
USR
NUMWORDS_A
128
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
36
PARAMETER_DEC
USR
WIDTHAD_B
7
PARAMETER_DEC
USR
NUMWORDS_B
128
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE

PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_gpm1
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
clock0
clock1
clocken0
clocken1
data_a0
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
data_a16
data_a17
data_a18
data_a19
data_a1
data_a20
data_a21
data_a22
data_a23
data_a24
data_a25
data_a26
data_a27
data_a28
data_a29
data_a2
data_a30
data_a31
data_a32
data_a33
data_a34
data_a35
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_b0
data_b10
data_b11
data_b12
data_b13
data_b14
data_b15
data_b16
data_b17
data_b18
data_b19
data_b1
data_b20
data_b21
data_b22
data_b23
data_b24
data_b25
data_b26
data_b27
data_b28
data_b29
data_b2
data_b30
data_b31
data_b32
data_b33
data_b34
data_b35
data_b3
data_b4
data_b5
data_b6
data_b7
data_b8
data_b9
q_a0
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_a16
q_a17
q_a18
q_a19
q_a1
q_a20
q_a21
q_a22
q_a23
q_a24
q_a25
q_a26
q_a27
q_a28
q_a29
q_a2
q_a30
q_a31
q_a32
q_a33
q_a34
q_a35
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_b0
q_b10
q_b11
q_b12
q_b13
q_b14
q_b15
q_b16
q_b17
q_b18
q_b19
q_b1
q_b20
q_b21
q_b22
q_b23
q_b24
q_b25
q_b26
q_b27
q_b28
q_b29
q_b2
q_b30
q_b31
q_b32
q_b33
q_b34
q_b35
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
wren_a
wren_b
}
# include_file {
d:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
d:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
d:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
d:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
d:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
d:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
d:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
d:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
d:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
d:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
first_nios2_system:inst|CPU:the_CPU|CPU_nios2_oci:the_CPU_nios2_oci|CPU_nios2_oci_im:the_CPU_nios2_oci_im|CPU_traceram_lpm_dram_bdp_component_module:CPU_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_gpm1
# case_insensitive
# source_file
db|altsyncram_gpm1.tdf
1144980382
6
# storage
db|Test_LED.(42).cnf
db|Test_LED.(42).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
wren_b
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
data_a16
data_a17
data_a18
data_a19
data_a20
data_a21
data_a22
data_a23
data_a24
data_a25
data_a26
data_a27
data_a28
data_a29
data_a30
data_a31
data_a32
data_a33
data_a34
data_a35
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
data_b8
data_b9
data_b10
data_b11
data_b12
data_b13
data_b14
data_b15
data_b16
data_b17
data_b18
data_b19
data_b20
data_b21
data_b22
data_b23
data_b24
data_b25
data_b26
data_b27
data_b28
data_b29
data_b30
data_b31
data_b32
data_b33
data_b34
data_b35
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
clock0
clock1
clocken0
clocken1
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_a16
q_a17
q_a18
q_a19
q_a20
q_a21
q_a22
q_a23
q_a24
q_a25
q_a26
q_a27
q_a28
q_a29
q_a30
q_a31
q_a32
q_a33
q_a34
q_a35
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
q_b10
q_b11
q_b12
q_b13
q_b14
q_b15
q_b16
q_b17
q_b18
q_b19
q_b20
q_b21
q_b22
q_b23
q_b24
q_b25
q_b26
q_b27
q_b28
q_b29
q_b30
q_b31
q_b32
q_b33
q_b34
q_b35
}
# memory_file {
none
0
}
# hierarchies {
first_nios2_system:inst|CPU:the_CPU|CPU_nios2_oci:the_CPU_nios2_oci|CPU_nios2_oci_im:the_CPU_nios2_oci_im|CPU_traceram_lpm_dram_bdp_component_module:CPU_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_gpm1:auto_generated
}
# end
# entity
CPU_jtag_debug_module_wrapper
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
CPU_jtag_debug_module_wrapper.vhd
1144980038
4
# storage
db|Test_LED.(43).cnf
db|Test_LED.(43).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
altera_vhdl_support.vhd
1144980097
}
# hierarchies {
first_nios2_system:inst|CPU:the_CPU|CPU_nios2_oci:the_CPU_nios2_oci|CPU_jtag_debug_module_wrapper:the_CPU_jtag_debug_module_wrapper
}
# end
# entity
CPU_jtag_debug_module
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
CPU_jtag_debug_module.vhd
1144980038
4
# storage
db|Test_LED.(44).cnf
db|Test_LED.(44).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_node_info
286279168
PARAMETER_DEC
USR
}
# include_file {
altera_vhdl_support.vhd
1144980097
}
# hierarchies {
first_nios2_system:inst|CPU:the_CPU|CPU_nios2_oci:the_CPU_nios2_oci|CPU_jtag_debug_module_wrapper:the_CPU_jtag_debug_module_wrapper|CPU_jtag_debug_module:the_CPU_jtag_debug_module1
}
# end
# entity
LED_PIO_s1_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
first_nios2_system.vhd
1144980106
4
# storage
db|Test_LED.(45).cnf
db|Test_LED.(45).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
altera_vhdl_support.vhd
1144980097
}
# hierarchies {
first_nios2_system:inst|LED_PIO_s1_arbitrator:the_LED_PIO_s1
}
# end
# entity
LED_PIO
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
LED_PIO.vhd
1144980086
4
# storage
db|Test_LED.(46).cnf
db|Test_LED.(46).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
altera_vhdl_support.vhd
1144980097
}
# hierarchies {
first_nios2_system:inst|LED_PIO:the_LED_PIO
}
# end
# entity
onchip_RAM_s1_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
first_nios2_system.vhd
1144980106
4
# storage
db|Test_LED.(47).cnf
db|Test_LED.(47).cnf