test_led.hier_info

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~13.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~14.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~15.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~16.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~17.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~18.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~19.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~20.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~21.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~22.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~23.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~24.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~25.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~26.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~27.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~28.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~29.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~30.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_readdata~31.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => r_0~1.IN0
CPU_instruction_master_qualified_request_CPU_jtag_debug_module => r_0~3.IN0
CPU_instruction_master_qualified_request_onchip_RAM_s1 => r_0~7.IN1
CPU_instruction_master_qualified_request_onchip_RAM_s1 => r_0~9.IN0
CPU_instruction_master_qualified_request_onchip_RAM_s1 => r_0~11.IN1
CPU_instruction_master_qualified_request_onchip_ROM_s1 => r_0~14.IN1
CPU_instruction_master_qualified_request_onchip_ROM_s1 => r_0~16.IN0
CPU_instruction_master_qualified_request_onchip_ROM_s1 => r_0~18.IN1
CPU_instruction_master_read => r_0~4.IN0
CPU_instruction_master_read => r_0~12.IN0
CPU_instruction_master_read => r_0~19.IN0
CPU_instruction_master_read => p1_CPU_instruction_master_latency_counter~0.IN0
CPU_instruction_master_read => r_0~3.IN1
CPU_instruction_master_read => r_0~11.IN0
CPU_instruction_master_read => r_0~18.IN0
CPU_instruction_master_read_data_valid_CPU_jtag_debug_module => CPU_instruction_master_readdatavalid~1.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => pre_flush_CPU_instruction_master_readdatavalid.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~32.IN1
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~33.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~34.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~35.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~36.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~37.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~38.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~39.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~40.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~41.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~42.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~43.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~44.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~45.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~46.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~47.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~48.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~49.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~50.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~51.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~52.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~53.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~54.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~55.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~56.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~57.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~58.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~59.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~60.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~61.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~62.IN0
CPU_instruction_master_read_data_valid_onchip_RAM_s1 => CPU_instruction_master_readdata~63.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => pre_flush_CPU_instruction_master_readdatavalid.IN1
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~96.IN1
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~97.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~98.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~99.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~100.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~101.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~102.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~103.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~104.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~105.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~106.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~107.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~108.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~109.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~110.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~111.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~112.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~113.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~114.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~115.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~116.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~117.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~118.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~119.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~120.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~121.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~122.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~123.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~124.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~125.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~126.IN0
CPU_instruction_master_read_data_valid_onchip_ROM_s1 => CPU_instruction_master_readdata~127.IN0
CPU_instruction_master_requests_CPU_jtag_debug_module => r_0~0.IN1
CPU_instruction_master_requests_onchip_RAM_s1 => latency_load_value.IN0
CPU_instruction_master_requests_onchip_RAM_s1 => r_0~7.IN0
CPU_instruction_master_requests_onchip_ROM_s1 => latency_load_value.IN1
CPU_instruction_master_requests_onchip_ROM_s1 => r_0~14.IN0
CPU_jtag_debug_module_readdata_from_sa[0] => CPU_instruction_master_readdata~0.IN1
CPU_jtag_debug_module_readdata_from_sa[1] => CPU_instruction_master_readdata~1.IN1
CPU_jtag_debug_module_readdata_from_sa[2] => CPU_instruction_master_readdata~2.IN1
CPU_jtag_debug_module_readdata_from_sa[3] => CPU_instruction_master_readdata~3.IN1
CPU_jtag_debug_module_readdata_from_sa[4] => CPU_instruction_master_readdata~4.IN1
CPU_jtag_debug_module_readdata_from_sa[5] => CPU_instruction_master_readdata~5.IN1
CPU_jtag_debug_module_readdata_from_sa[6] => CPU_instruction_master_readdata~6.IN1
CPU_jtag_debug_module_readdata_from_sa[7] => CPU_instruction_master_readdata~7.IN1
CPU_jtag_debug_module_readdata_from_sa[8] => CPU_instruction_master_readdata~8.IN1
CPU_jtag_debug_module_readdata_from_sa[9] => CPU_instruction_master_readdata~9.IN1
CPU_jtag_debug_module_readdata_from_sa[10] => CPU_instruction_master_readdata~10.IN1
CPU_jtag_debug_module_readdata_from_sa[11] => CPU_instruction_master_readdata~11.IN1
CPU_jtag_debug_module_readdata_from_sa[12] => CPU_instruction_master_readdata~12.IN1
CPU_jtag_debug_module_readdata_from_sa[13] => CPU_instruction_master_readdata~13.IN1
CPU_jtag_debug_module_readdata_from_sa[14] => CPU_instruction_master_readdata~14.IN1
CPU_jtag_debug_module_readdata_from_sa[15] => CPU_instruction_master_readdata~15.IN1
CPU_jtag_debug_module_readdata_from_sa[16] => CPU_instruction_master_readdata~16.IN1
CPU_jtag_debug_module_readdata_from_sa[17] => CPU_instruction_master_readdata~17.IN1
CPU_jtag_debug_module_readdata_from_sa[18] => CPU_instruction_master_readdata~18.IN1
CPU_jtag_debug_module_readdata_from_sa[19] => CPU_instruction_master_readdata~19.IN1
CPU_jtag_debug_module_readdata_from_sa[20] => CPU_instruction_master_readdata~20.IN1
CPU_jtag_debug_module_readdata_from_sa[21] => CPU_instruction_master_readdata~21.IN1
CPU_jtag_debug_module_readdata_from_sa[22] => CPU_instruction_master_readdata~22.IN1
CPU_jtag_debug_module_readdata_from_sa[23] => CPU_instruction_master_readdata~23.IN1
CPU_jtag_debug_module_readdata_from_sa[24] => CPU_instruction_master_readdata~24.IN1
CPU_jtag_debug_module_readdata_from_sa[25] => CPU_instruction_master_readdata~25.IN1
CPU_jtag_debug_module_readdata_from_sa[26] => CPU_instruction_master_readdata~26.IN1
CPU_jtag_debug_module_readdata_from_sa[27] => CPU_instruction_master_readdata~27.IN1
CPU_jtag_debug_module_readdata_from_sa[28] => CPU_instruction_master_readdata~28.IN1
CPU_jtag_debug_module_readdata_from_sa[29] => CPU_instruction_master_readdata~29.IN1
CPU_jtag_debug_module_readdata_from_sa[30] => CPU_instruction_master_readdata~30.IN1
CPU_jtag_debug_module_readdata_from_sa[31] => CPU_instruction_master_readdata~31.IN1
clk => internal_CPU_instruction_master_latency_counter.CLK
clk => CPU_instruction_master_read_but_no_slave_selected.CLK
d1_CPU_jtag_debug_module_end_xfer => r_0~4.IN1
d1_onchip_RAM_s1_end_xfer => ~NO_FANOUT~
d1_onchip_ROM_s1_end_xfer => ~NO_FANOUT~
onchip_RAM_s1_readdata_from_sa[0] => CPU_instruction_master_readdata~32.IN0
onchip_RAM_s1_readdata_from_sa[1] => CPU_instruction_master_readdata~33.IN1
onchip_RAM_s1_readdata_from_sa[2] => CPU_instruction_master_readdata~34.IN1
onchip_RAM_s1_readdata_from_sa[3] => CPU_instruction_master_readdata~35.IN1
onchip_RAM_s1_readdata_from_sa[4] => CPU_instruction_master_readdata~36.IN1
onchip_RAM_s1_readdata_from_sa[5] => CPU_instruction_master_readdata~37.IN1
onchip_RAM_s1_readdata_from_sa[6] => CPU_instruction_master_readdata~38.IN1
onchip_RAM_s1_readdata_from_sa[7] => CPU_instruction_master_readdata~39.IN1
onchip_RAM_s1_readdata_from_sa[8] => CPU_instruction_master_readdata~40.IN1
onchip_RAM_s1_readdata_from_sa[9] => CPU_instruction_master_readdata~41.IN1
onchip_RAM_s1_readdata_from_sa[10] => CPU_instruction_master_readdata~42.IN1
onchip_RAM_s1_readdata_from_sa[11] => CPU_instruction_master_readdata~43.IN1
onchip_RAM_s1_readdata_from_sa[12] => CPU_instruction_master_readdata~44.IN1
onchip_RAM_s1_readdata_from_sa[13] => CPU_instruction_master_readdata~45.IN1
onchip_RAM_s1_readdata_from_sa[14] => CPU_instruction_master_readdata~46.IN1
onchip_RAM_s1_readdata_from_sa[15] => CPU_instruction_master_readdata~47.IN1
onchip_RAM_s1_readdata_from_sa[16] => CPU_instruction_master_readdata~48.IN1
onchip_RAM_s1_readdata_from_sa[17] => CPU_instruction_master_readdata~49.IN1
onchip_RAM_s1_readdata_from_sa[18] => CPU_instruction_master_readdata~50.IN1
onchip_RAM_s1_readdata_from_sa[19] => CPU_instruction_master_readdata~51.IN1
onchip_RAM_s1_readdata_from_sa[20] => CPU_instruction_