test_led.hier_info

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

|Test_LED
LED_PIO <= first_nios2_system:inst.out_port_from_the_LED_PIO
CLK => first_nios2_system:inst.clk
nRST => first_nios2_system:inst.reset_n


|Test_LED|first_nios2_system:inst
clk => first_nios2_system_reset_clk_domain_synch_module:first_nios2_system_reset_clk_domain_synch.clk
clk => sysid_control_slave_arbitrator:the_sysid_control_slave.clk
clk => onchip_ROM:the_onchip_ROM.clk
clk => onchip_ROM_s1_arbitrator:the_onchip_ROM_s1.clk
clk => onchip_RAM:the_onchip_RAM.clk
clk => onchip_RAM_s1_arbitrator:the_onchip_RAM_s1.clk
clk => LED_PIO:the_LED_PIO.clk
clk => LED_PIO_s1_arbitrator:the_LED_PIO_s1.clk
clk => CPU:the_CPU.jtag_debug_module_clk
clk => CPU:the_CPU.clk
clk => CPU_instruction_master_arbitrator:the_CPU_instruction_master.clk
clk => CPU_data_master_arbitrator:the_CPU_data_master.clk
clk => CPU_jtag_debug_module_arbitrator:the_CPU_jtag_debug_module.clk
reset_n => reset_n_sources~0.IN1
out_port_from_the_LED_PIO <= LED_PIO:the_LED_PIO.out_port


|Test_LED|first_nios2_system:inst|CPU_jtag_debug_module_arbitrator:the_CPU_jtag_debug_module
CPU_data_master_address_to_slave[0] => ~NO_FANOUT~
CPU_data_master_address_to_slave[1] => ~NO_FANOUT~
CPU_data_master_address_to_slave[2] => A_WE_StdLogicVector~15.DATAB
CPU_data_master_address_to_slave[3] => A_WE_StdLogicVector~14.DATAB
CPU_data_master_address_to_slave[4] => A_WE_StdLogicVector~13.DATAB
CPU_data_master_address_to_slave[5] => A_WE_StdLogicVector~12.DATAB
CPU_data_master_address_to_slave[6] => A_WE_StdLogicVector~11.DATAB
CPU_data_master_address_to_slave[7] => A_WE_StdLogicVector~10.DATAB
CPU_data_master_address_to_slave[8] => A_WE_StdLogicVector~9.DATAB
CPU_data_master_address_to_slave[9] => A_WE_StdLogicVector~8.DATAB
CPU_data_master_address_to_slave[10] => A_WE_StdLogicVector~7.DATAB
CPU_data_master_address_to_slave[11] => reduce_nor~0.IN1
CPU_data_master_address_to_slave[12] => reduce_nor~0.IN0
CPU_data_master_byteenable[0] => A_WE_StdLogicVector~19.DATAB
CPU_data_master_byteenable[1] => A_WE_StdLogicVector~18.DATAB
CPU_data_master_byteenable[2] => A_WE_StdLogicVector~17.DATAB
CPU_data_master_byteenable[3] => A_WE_StdLogicVector~16.DATAB
CPU_data_master_debugaccess => CPU_jtag_debug_module_debugaccess.DATAIN
CPU_data_master_read => internal_CPU_data_master_requests_CPU_jtag_debug_module~0.IN0
CPU_data_master_read => CPU_jtag_debug_module_in_a_read_cycle~0.IN0
CPU_data_master_write => internal_CPU_data_master_requests_CPU_jtag_debug_module~0.IN1
CPU_data_master_write => CPU_jtag_debug_module_write~0.IN0
CPU_data_master_write => CPU_jtag_debug_module_in_a_write_cycle.IN0
CPU_data_master_writedata[0] => CPU_jtag_debug_module_writedata[0].DATAIN
CPU_data_master_writedata[1] => CPU_jtag_debug_module_writedata[1].DATAIN
CPU_data_master_writedata[2] => CPU_jtag_debug_module_writedata[2].DATAIN
CPU_data_master_writedata[3] => CPU_jtag_debug_module_writedata[3].DATAIN
CPU_data_master_writedata[4] => CPU_jtag_debug_module_writedata[4].DATAIN
CPU_data_master_writedata[5] => CPU_jtag_debug_module_writedata[5].DATAIN
CPU_data_master_writedata[6] => CPU_jtag_debug_module_writedata[6].DATAIN
CPU_data_master_writedata[7] => CPU_jtag_debug_module_writedata[7].DATAIN
CPU_data_master_writedata[8] => CPU_jtag_debug_module_writedata[8].DATAIN
CPU_data_master_writedata[9] => CPU_jtag_debug_module_writedata[9].DATAIN
CPU_data_master_writedata[10] => CPU_jtag_debug_module_writedata[10].DATAIN
CPU_data_master_writedata[11] => CPU_jtag_debug_module_writedata[11].DATAIN
CPU_data_master_writedata[12] => CPU_jtag_debug_module_writedata[12].DATAIN
CPU_data_master_writedata[13] => CPU_jtag_debug_module_writedata[13].DATAIN
CPU_data_master_writedata[14] => CPU_jtag_debug_module_writedata[14].DATAIN
CPU_data_master_writedata[15] => CPU_jtag_debug_module_writedata[15].DATAIN
CPU_data_master_writedata[16] => CPU_jtag_debug_module_writedata[16].DATAIN
CPU_data_master_writedata[17] => CPU_jtag_debug_module_writedata[17].DATAIN
CPU_data_master_writedata[18] => CPU_jtag_debug_module_writedata[18].DATAIN
CPU_data_master_writedata[19] => CPU_jtag_debug_module_writedata[19].DATAIN
CPU_data_master_writedata[20] => CPU_jtag_debug_module_writedata[20].DATAIN
CPU_data_master_writedata[21] => CPU_jtag_debug_module_writedata[21].DATAIN
CPU_data_master_writedata[22] => CPU_jtag_debug_module_writedata[22].DATAIN
CPU_data_master_writedata[23] => CPU_jtag_debug_module_writedata[23].DATAIN
CPU_data_master_writedata[24] => CPU_jtag_debug_module_writedata[24].DATAIN
CPU_data_master_writedata[25] => CPU_jtag_debug_module_writedata[25].DATAIN
CPU_data_master_writedata[26] => CPU_jtag_debug_module_writedata[26].DATAIN
CPU_data_master_writedata[27] => CPU_jtag_debug_module_writedata[27].DATAIN
CPU_data_master_writedata[28] => CPU_jtag_debug_module_writedata[28].DATAIN
CPU_data_master_writedata[29] => CPU_jtag_debug_module_writedata[29].DATAIN
CPU_data_master_writedata[30] => CPU_jtag_debug_module_writedata[30].DATAIN
CPU_data_master_writedata[31] => CPU_jtag_debug_module_writedata[31].DATAIN
CPU_instruction_master_address_to_slave[0] => ~NO_FANOUT~
CPU_instruction_master_address_to_slave[1] => ~NO_FANOUT~
CPU_instruction_master_address_to_slave[2] => A_WE_StdLogicVector~15.DATAA
CPU_instruction_master_address_to_slave[3] => A_WE_StdLogicVector~14.DATAA
CPU_instruction_master_address_to_slave[4] => A_WE_StdLogicVector~13.DATAA
CPU_instruction_master_address_to_slave[5] => A_WE_StdLogicVector~12.DATAA
CPU_instruction_master_address_to_slave[6] => A_WE_StdLogicVector~11.DATAA
CPU_instruction_master_address_to_slave[7] => A_WE_StdLogicVector~10.DATAA
CPU_instruction_master_address_to_slave[8] => A_WE_StdLogicVector~9.DATAA
CPU_instruction_master_address_to_slave[9] => A_WE_StdLogicVector~8.DATAA
CPU_instruction_master_address_to_slave[10] => A_WE_StdLogicVector~7.DATAA
CPU_instruction_master_address_to_slave[11] => reduce_nor~1.IN1
CPU_instruction_master_address_to_slave[12] => reduce_nor~1.IN0
CPU_instruction_master_latency_counter => internal_CPU_instruction_master_qualified_request_CPU_jtag_debug_module~0.IN1
CPU_instruction_master_read => internal_CPU_instruction_master_requests_CPU_jtag_debug_module~0.IN0
CPU_instruction_master_read => internal_CPU_instruction_master_qualified_request_CPU_jtag_debug_module~0.IN0
CPU_instruction_master_read => CPU_instruction_master_read_data_valid_CPU_jtag_debug_module~0.IN0
CPU_jtag_debug_module_readdata[0] => CPU_jtag_debug_module_readdata_from_sa[0].DATAIN
CPU_jtag_debug_module_readdata[1] => CPU_jtag_debug_module_readdata_from_sa[1].DATAIN
CPU_jtag_debug_module_readdata[2] => CPU_jtag_debug_module_readdata_from_sa[2].DATAIN
CPU_jtag_debug_module_readdata[3] => CPU_jtag_debug_module_readdata_from_sa[3].DATAIN
CPU_jtag_debug_module_readdata[4] => CPU_jtag_debug_module_readdata_from_sa[4].DATAIN
CPU_jtag_debug_module_readdata[5] => CPU_jtag_debug_module_readdata_from_sa[5].DATAIN
CPU_jtag_debug_module_readdata[6] => CPU_jtag_debug_module_readdata_from_sa[6].DATAIN
CPU_jtag_debug_module_readdata[7] => CPU_jtag_debug_module_readdata_from_sa[7].DATAIN
CPU_jtag_debug_module_readdata[8] => CPU_jtag_debug_module_readdata_from_sa[8].DATAIN
CPU_jtag_debug_module_readdata[9] => CPU_jtag_debug_module_readdata_from_sa[9].DATAIN
CPU_jtag_debug_module_readdata[10] => CPU_jtag_debug_module_readdata_from_sa[10].DATAIN
CPU_jtag_debug_module_readdata[11] => CPU_jtag_debug_module_readdata_from_sa[11].DATAIN
CPU_jtag_debug_module_readdata[12] => CPU_jtag_debug_module_readdata_from_sa[12].DATAIN
CPU_jtag_debug_module_readdata[13] => CPU_jtag_debug_module_readdata_from_sa[13].DATAIN
CPU_jtag_debug_module_readdata[14] => CPU_jtag_debug_module_readdata_from_sa[14].DATAIN
CPU_jtag_debug_module_readdata[15] => CPU_jtag_debug_module_readdata_from_sa[15].DATAIN
CPU_jtag_debug_module_readdata[16] => CPU_jtag_debug_module_readdata_from_sa[16].DATAIN
CPU_jtag_debug_module_readdata[17] => CPU_jtag_debug_module_readdata_from_sa[17].DATAIN
CPU_jtag_debug_module_readdata[18] => CPU_jtag_debug_module_readdata_from_sa[18].DATAIN
CPU_jtag_debug_module_readdata[19] => CPU_jtag_debug_module_readdata_from_sa[19].DATAIN
CPU_jtag_debug_module_readdata[20] => CPU_jtag_debug_module_readdata_from_sa[20].DATAIN
CPU_jtag_debug_module_readdata[21] => CPU_jtag_debug_module_readdata_from_sa[21].DATAIN
CPU_jtag_debug_module_readdata[22] => CPU_jtag_debug_module_readdata_from_sa[22].DATAIN
CPU_jtag_debug_module_readdata[23] => CPU_jtag_debug_module_readdata_from_sa[23].DATAIN
CPU_jtag_debug_module_readdata[24] => CPU_jtag_debug_module_readdata_from_sa[24].DATAIN
CPU_jtag_debug_module_readdata[25] => CPU_jtag_debug_module_readdata_from_sa[25].DATAIN
CPU_jtag_debug_module_readdata[26] => CPU_jtag_debug_module_readdata_from_sa[26].DATAIN
CPU_jtag_debug_module_readdata[27] => CPU_jtag_debug_module_readdata_from_sa[27].DATAIN
CPU_jtag_debug_module_readdata[28] => CPU_jtag_debug_module_readdata_from_sa[28].DATAIN
CPU_jtag_debug_module_readdata[29] => CPU_jtag_debug_module_readdata_from_sa[29].DATAIN
CPU_jtag_debug_module_readdata[30] => CPU_jtag_debug_module_readdata_from_sa[30].DATAIN
CPU_jtag_debug_module_readdata[31] => CPU_jtag_debug_module_readdata_from_sa[31].DATAIN
CPU_jtag_debug_module_resetrequest => CPU_jtag_debug_module_resetrequest_from_sa.DATAIN
clk => CPU_jtag_debug_module_arb_share_counter.CLK
clk => CPU_jtag_debug_module_slavearbiterlockenable.CLK
clk => last_cycle_CPU_instruction_master_granted_slave_CPU_jtag_debug_module.CLK
clk => last_cycle_CPU_data_master_granted_slave_CPU_jtag_debug_module.CLK
clk => CPU_jtag_debug_module_saved_chosen_master_vector[1].CLK
clk => CPU_jtag_debug_module_saved_chosen_master_vector[0].CLK
clk => CPU_jtag_debug_module_arb_addend[1].CLK
clk => CPU_jtag_debug_module_arb_addend[0].CLK
clk => d1_CPU_jtag_debug_module_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
reset_n => CPU_jtag_debug_module_reset_n.DATAIN
reset_n => d1_CPU_jtag_debug_module_end_xfer~reg0.PRESET
reset_n => CPU_jtag_debug_module_arb_share_counter.ACLR
reset_n => CPU_jtag_debug_module_slavearbiterlockenable.ACLR
reset_n => last_cycle_CPU_instruction_master_granted_slave_CPU_jtag_debug_module.ACLR
reset_n => last_cycle_CPU_data_master_granted_slave_CPU_jtag_debug_module.ACLR
reset_n => CPU_jtag_debug_module_saved_chosen_master_vector[0].ACLR
reset_n => CPU_jtag_debug_module_saved_chosen_master_vector[1].ACLR
reset_n => CPU_jtag_debug_module_arb_addend[0].PRESET
reset_n => CPU_jtag_debug_module_arb_addend[1].ACLR
reset_n => d1_reasons_to_wait.ACLR
reset_n => CPU_jtag_debug_module_reset.DATAIN
CPU_data_master_granted_CPU_jtag_debug_module <= CPU_jtag_debug_module_grant_vector~0.DB_MAX_OUTPUT_PORT_TYPE
CPU_data_master_qualified_request_CPU_jtag_debug_module <= internal_CPU_data_master_qualified_request_CPU_jtag_debug_module~0.DB_MAX_OUTPUT_PORT_TYPE
CPU_data_master_read_data_valid_CPU_jtag_debug_module <= <GND>
CPU_data_master_requests_CPU_jtag_debug_module <= internal_CPU_data_master_requests_CPU_jtag_debug_module~1.DB_MAX_OUTPUT_PORT_TYPE
CPU_instruction_master_granted_CPU_jtag_debug_module <= CPU_jtag_debug_module_grant_vector~1.DB_MAX_OUTPUT_PORT_TYPE
CPU_instruction_master_qualified_request_CPU_jtag_debug_module <= internal_CPU_instruction_master_qualified_request_CPU_jtag_debug_module~2.DB_MAX_OUTPUT_PORT_TYPE
CPU_instruction_master_read_data_valid_CPU_jtag_debug_module <= CPU_instruction_master_read_data_valid_CPU_jtag_debug_module~1.DB_MAX_OUTPUT_PORT_TYPE
CPU_instruction_master_requests_CPU_jtag_debug_module <= internal_CPU_instruction_master_requests_CPU_jtag_debug_module~0.DB_MAX_OUTPUT_PORT_TYPE
CPU_jtag_debug_module_address[0] <= A_WE_StdLogicVector~15.DB_MAX_OUTPUT_PORT_TYPE
CPU_jtag_debug_module_address[1] <= A_WE_StdLogicVector~14.DB_MAX_OUTPUT_PORT_TYPE
CPU_jtag_debug_module_address[2] <= A_WE_StdLogicVector~13.DB_MAX_OUTPUT_PORT_TYPE
CPU_jtag_debug_module_address[3] <= A_WE_StdLogicVector~12.DB_MAX_OUTPUT_PORT_TYPE
CPU_jtag_debug_module_address[4] <= A_WE_StdLogicVector~11.DB_MAX_OUTPUT_PORT_TYPE
CPU_jtag_debug_module_address[5] <= A_WE_StdLogicVector~10.DB_MAX_OUTPUT_PORT_TYPE