test_led.fit.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.369 ns register register " "Info: Estimated most critical path is register to register delay of 2.369 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 1 REG LAB_X9_Y10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y10; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" {  } { { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(0.442 ns) 1.519 ns sld_hub:sld_hub_inst\|hub_tdo~231 2 COMB LAB_X10_Y12 1 " "Info: 2: + IC(1.077 ns) + CELL(0.442 ns) = 1.519 ns; Loc. = LAB_X10_Y12; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~231'" {  } { { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "1.519 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~231 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.478 ns) 2.369 ns sld_hub:sld_hub_inst\|hub_tdo 3 REG LAB_X10_Y12 0 " "Info: 3: + IC(0.372 ns) + CELL(0.478 ns) = 2.369 ns; Loc. = LAB_X10_Y12; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "0.850 ns" { sld_hub:sld_hub_inst|hub_tdo~231 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.920 ns 38.83 % " "Info: Total cell delay = 0.920 ns ( 38.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.449 ns 61.17 % " "Info: Total interconnect delay = 1.449 ns ( 61.17 % )" {  } {  } 0}  } { { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "2.369 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~231 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:05 " "Info: Fitter placement operations ending: elapsed time is 00:00:05" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "15 33 " "Info: Average interconnect usage is 15% of the available device resources. Peak interconnect usage is 33%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:06 " "Info: Fitter routing operations ending: elapsed time is 00:00:06" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "altera_internal_jtag " "Info: Node altera_internal_jtag uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear first_nios2_system:inst\|CPU:the_CPU\|CPU_nios2_oci:the_CPU_nios2_oci\|CPU_jtag_debug_module_wrapper:the_CPU_jtag_debug_module_wrapper\|CPU_jtag_debug_module:the_CPU_jtag_debug_module1\|st_shiftdr " "Info: Port clear -- assigned as a global for destination node first_nios2_system:inst\|CPU:the_CPU\|CPU_nios2_oci:the_CPU_nios2_oci\|CPU_jtag_debug_module_wrapper:the_CPU_jtag_debug_module_wrapper\|CPU_jtag_debug_module:the_CPU_jtag_debug_module1\|st_shiftdr -- routed using non-global resources" {  } { { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { first_nios2_system:inst|CPU:the_CPU|CPU_nios2_oci:the_CPU_nios2_oci|CPU_jtag_debug_module_wrapper:the_CPU_jtag_debug_module_wrapper|CPU_jtag_debug_module:the_CPU_jtag_debug_module1|st_shiftdr } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "first_nios2_system:inst\|CPU:the_CPU\|CPU_nios2_oci:the_CPU_nios2_oci\|CPU_jtag_debug_module_wrapper:the_CPU_jtag_debug_module_wrapper\|CPU_jtag_debug_module:the_CPU_jtag_debug_module1\|st_shiftdr" } } } } { "CPU_jtag_debug_module.vhd" "" { Text "E:/QProj/Test_LED/CPU_jtag_debug_module.vhd" 79 -1 0 } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { first_nios2_system:inst|CPU:the_CPU|CPU_nios2_oci:the_CPU_nios2_oci|CPU_jtag_debug_module_wrapper:the_CPU_jtag_debug_module_wrapper|CPU_jtag_debug_module:the_CPU_jtag_debug_module1|st_shiftdr } "NODE_NAME" } }  } 0}  } { { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "first_nios2_system:inst\|first_nios2_system_reset_clk_domain_synch_module:first_nios2_system_reset_clk_domain_synch\|data_out " "Info: Node first_nios2_system:inst\|first_nios2_system_reset_clk_domain_synch_module:first_nios2_system_reset_clk_domain_synch\|data_out uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear first_nios2_system:inst\|CPU_jtag_debug_module_arbitrator:the_CPU_jtag_debug_module\|d1_reasons_to_wait " "Info: Port clear -- assigned as a global for destination node first_nios2_system:inst\|CPU_jtag_debug_module_arbitrator:the_CPU_jtag_debug_module\|d1_reasons_to_wait -- routed using non-global resources" {  } { { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { first_nios2_system:inst|CPU_jtag_debug_module_arbitrator:the_CPU_jtag_debug_module|d1_reasons_to_wait } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "first_nios2_system:inst\|CPU_jtag_debug_module_arbitrator:the_CPU_jtag_debug_module\|d1_reasons_to_wait" } } } } { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 104 -1 0 } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { first_nios2_system:inst|CPU_jtag_debug_module_arbitrator:the_CPU_jtag_debug_module|d1_reasons_to_wait } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear first_nios2_system:inst\|CPU:the_CPU\|wait_for_one_post_bret_inst " "Info: Port clear -- assigned as a global for destination node first_nios2_system:inst\|CPU:the_CPU\|wait_for_one_post_bret_inst -- routed using non-global resources" {  } { { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { first_nios2_system:inst|CPU:the_CPU|wait_for_one_post_bret_inst } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "first_nios2_system:inst\|CPU:the_CPU\|wait_for_one_post_bret_inst" } } } } { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 5692 -1 0 } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { first_nios2_system:inst|CPU:the_CPU|wait_for_one_post_bret_inst } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear first_nios2_system:inst\|CPU:the_CPU\|latched_oci_tb_hbreak_req " "Info: Port clear -- assigned as a global for destination node first_nios2_system:inst\|CPU:the_CPU\|latched_oci_tb_hbreak_req -- routed using non-global resources" {  } { { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { first_nios2_system:inst|CPU:the_CPU|latched_oci_tb_hbreak_req } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "first_nios2_system:inst\|CPU:the_CPU\|latched_oci_tb_hbreak_req" } } } } { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 5684 -1 0 } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { first_nios2_system:inst|CPU:the_CPU|latched_oci_tb_hbreak_req } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear first_nios2_system:inst\|CPU:the_CPU\|E_iw\[15\] " "Info: Port clear -- assigned as a global for destination node first_nios2_system:inst\|CPU:the_CPU\|E_iw\[15\] -- routed using non-global resources" {  } { { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { first_nios2_system:inst|CPU:the_CPU|E_iw[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "first_nios2_system:inst\|CPU:the_CPU\|E_iw\[15\]" } } } } { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 4900 -1 0 } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { first_nios2_system:inst|CPU:the_CPU|E_iw[15] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear first_nios2_system:inst\|CPU:the_CPU\|E_iw\[13\] " "Info: Port clear -- assigned as a global for destination node first_nios2_system:inst\|CPU:the_CPU\|E_iw\[13\] -- routed using non-global resources" {  } { { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { first_nios2_system:inst|CPU:the_CPU|E_iw[13] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "first_nios2_system:inst\|CPU:the_CPU\|E_iw\[13\]" } } } } { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 4900 -1 0 } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { first_nios2_system:inst|CPU:the_CPU|E_iw[13] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear first_nios2_system:inst\|CPU:the_CPU\|i_readdatavalid_d1 " "Info: Port clear -- assigned as a global for destination node first_nios2_system:inst\|CPU:the_CPU\|i_readdatavalid_d1 -- routed using non-global resources" {  } { { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { first_nios2_system:inst|CPU:the_CPU|i_readdatavalid_d1 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "first_nios2_system:inst\|CPU:the_CPU\|i_readdatavalid_d1" } } } } { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 5649 -1 0 } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { first_nios2_system:inst|CPU:the_CPU|i_readdatavalid_d1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear first_nios2_system:inst\|CPU:the_CPU\|M_ctrl_invalidate_i " "Info: Port clear -- assigned as a global for destination node first_nios2_system:inst\|CPU:the_CPU\|M_ctrl_invalidate_i -- routed using non-global resources" {  } { { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { first_nios2_system:inst|CPU:the_CPU|M_ctrl_invalidate_i } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "first_nios2_system:inst\|CPU:the_CPU\|M_ctrl_invalidate_i" } } } } { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 5273 -1 0 } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { first_nios2_system:inst|CPU:the_CPU|M_ctrl_invalidate_i } "NODE_NAME" } }  } 0}  } { { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { first_nios2_system:inst|first_nios2_system_reset_clk_domain_synch_module:first_nios2_system_reset_clk_domain_synch|data_out } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "first_nios2_system:inst\|first_nios2_system_reset_clk_domain_synch_module:first_nios2_system_reset_clk_domain_synch\|data_out" } } } } { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 1802 -1 0 } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { first_nios2_system:inst|first_nios2_system_reset_clk_domain_synch_module:first_nios2_system_reset_clk_domain_synch|data_out } "NODE_NAME" } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 10:07:49 2006 " "Info: Processing ended: Fri Apr 14 10:07:49 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:42 " "Info: Elapsed time: 00:00:42" {  } {  } 0}  } {  } 0}