test_led.fit.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 10:07:07 2006 " "Info: Processing started: Fri Apr 14 10:07:07 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off Test_LED -c Test_LED " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off Test_LED -c Test_LED" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "Test_LED EP1C6F256C8 " "Info: Selected device EP1C6F256C8 for design \"Test_LED\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12F256C8 " "Info: Device EP1C12F256C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "4 7 " "Info: No exact pin location assignment(s) for 4 pins of 7 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdo " "Info: Pin altera_reserved_tdo not assigned to an exact location on the device" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdo" } } } } { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { altera_reserved_tdo } "NODE_NAME" } "" } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { altera_reserved_tdo } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tms " "Info: Pin altera_reserved_tms not assigned to an exact location on the device" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tms" } } } } { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { altera_reserved_tms } "NODE_NAME" } "" } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { altera_reserved_tms } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tck " "Info: Pin altera_reserved_tck not assigned to an exact location on the device" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tck" } } } } { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { altera_reserved_tck } "NODE_NAME" } "" } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { altera_reserved_tck } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdi " "Info: Pin altera_reserved_tdi not assigned to an exact location on the device" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdi" } } } } { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { altera_reserved_tdi } "NODE_NAME" } "" } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { altera_reserved_tdi } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock in PIN G1 " "Info: Automatically promoted signal \"CLK\" to use Global clock in PIN G1" {  } { { "Test_LED.bdf" "" { Schematic "E:/QProj/Test_LED/Test_LED.bdf" { { 88 -16 152 104 "CLK" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~TCKUTAP\" to use Global clock" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~UPDATEUSER Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~UPDATEUSER\" to use Global clock" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" "" { Report "E:/QProj/Test_LED/db/Test_LED_cmp.qrpt" Compiler "Test_LED" "UNKNOWN" "V1" "E:/QProj/Test_LED/db/Test_LED.quartus_db" { Floorplan "E:/QProj/Test_LED/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "E:/QProj/Test_LED/Test_LED.fld" "" { Floorplan "E:/QProj/Test_LED/Test_LED.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "first_nios2_system:inst\|first_nios2_system_reset_clk_domain_synch_module:first_nios2_system_reset_clk_domain_synch\|data_out Global clock " "Info: Automatically promoted some destinations of signal \"first_nios2_system:inst\|first_nios2_system_reset_clk_domain_synch_module:first_nios2_system_reset_clk_domain_synch\|data_out\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "first_nios2_system:inst\|CPU:the_CPU\|CPU_nios2_oci:the_CPU_nios2_oci\|CPU_nios2_oci_debug:the_CPU_nios2_oci_debug\|jtag_break " "Info: Destination \"first_nios2_system:inst\|CPU:the_CPU\|CPU_nios2_oci:the_CPU_nios2_oci\|CPU_nios2_oci_debug:the_CPU_nios2_oci_debug\|jtag_break\" may be non-global or may not use global clock" {  } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 716 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wren " "Info: Destination \"first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wren\" may be non-global or may not use global clock" {  } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 5673 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wraddress\[0\]~791 " "Info: Destination \"first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wraddress\[0\]~791\" may be non-global or may not use global clock" {  } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 5670 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wraddress\[1\]~792 " "Info: Destination \"first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wraddress\[1\]~792\" may be non-global or may not use global clock" {  } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 5670 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wraddress\[2\]~793 " "Info: Destination \"first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wraddress\[2\]~793\" may be non-global or may not use global clock" {  } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 5670 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wraddress\[3\]~794 " "Info: Destination \"first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wraddress\[3\]~794\" may be non-global or may not use global clock" {  } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 5670 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wraddress\[4\]~795 " "Info: Destination \"first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wraddress\[4\]~795\" may be non-global or may not use global clock" {  } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 5670 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wraddress\[5\]~796 " "Info: Destination \"first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wraddress\[5\]~796\" may be non-global or may not use global clock" {  } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 5670 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wrdata\[5\]~184 " "Info: Destination \"first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wrdata\[5\]~184\" may be non-global or may not use global clock" {  } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 5671 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wrdata\[6\]~185 " "Info: Destination \"first_nios2_system:inst\|CPU:the_CPU\|ic_tag_wrdata\[6\]~185\" may be non-global or may not use global clock" {  } { { "CPU.vhd" "" { Text "E:/QProj/Test_LED/CPU.vhd" 5671 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "first_nios2_system.vhd" "" { Text "E:/QProj/Test_LED/first_nios2_system.vhd" 1802 -1 0 } }  } 0}