wave_presets.do

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

# Display signals from module onchip_ROM
add wave -noupdate -divider {onchip_ROM}
add wave -noupdate -format Logic /test_bench/DUT/the_onchip_ROM/chipselect
add wave -noupdate -format Logic /test_bench/DUT/the_onchip_ROM/write
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_onchip_ROM/address
add wave -noupdate -format Literal -radix binary /test_bench/DUT/the_onchip_ROM/byteenable
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_onchip_ROM/readdata
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_onchip_ROM/writedata


# Display signals from module CPU
add wave -noupdate -divider {CPU}
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/i_readdata
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/i_readdatavalid
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/i_waitrequest
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/i_address
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/i_read
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/clk
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/reset_n
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_readdata
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_waitrequest
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_irq
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_address
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_byteenable
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_read
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_write
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/d_writedata
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/the_CPU_test_bench/W_pcb
add wave -noupdate -format Logic -radix ascii /test_bench/DUT/the_CPU/the_CPU_test_bench/W_vinst
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/the_CPU_test_bench/W_valid
add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_CPU/the_CPU_test_bench/W_iw


# Display signals from module onchip_RAM
add wave -noupdate -divider {onchip_RAM}
add wave -noupdate -format Logic /test_bench/DUT/the_onchip_RAM/chipselect
add wave -noupdate -format Logic /test_bench/DUT/the_onchip_RAM/write
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_onchip_RAM/address
add wave -noupdate -format Literal -radix binary /test_bench/DUT/the_onchip_RAM/byteenable
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_onchip_RAM/readdata
add wave -noupdate -format Literal -radix hexadecimal /test_bench/DUT/the_onchip_RAM/writedata


configure wave -justifyvalue right
configure wave -signalnamewidth 1
TreeUpdate [SetDefaultTree]