standard.map.rpt

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

Analysis & Synthesis report for standard
Thu Nov 24 14:54:31 2005
Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Parameter Settings for User Entity Instance: PLL:inst|altpll:altpll_component
  6. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data
  7. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram
  8. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag
  9. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram
 10. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a
 11. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram
 12. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b
 13. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram
 14. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add
 15. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add|mult_add_ovq2:auto_generated|alt_mac_mult:mac_mult1
 16. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add|mult_add_ovq2:auto_generated|alt_mac_out:mac_out2
 17. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component
 18. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 19. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component
 20. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 21. Parameter Settings for User Entity Instance: standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1
 22. Parameter Settings for User Entity Instance: standard_1c6:inst3|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom
 23. Parameter Settings for User Entity Instance: standard_1c6:inst3|i2c_master:the_i2c_master|oc_i2c_master:the_oc_i2c_master|i2c_master_top:i2c_top_inst
 24. Parameter Settings for User Entity Instance: standard_1c6:inst3|i2c_master:the_i2c_master|oc_i2c_master:the_oc_i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1
 25. Parameter Settings for User Entity Instance: standard_1c6:inst3|i2c_master:the_i2c_master|oc_i2c_master:the_oc_i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|i2c_master_bit_ctrl:u1
 26. Parameter Settings for User Entity Instance: standard_1c6:inst3|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo
 27. Parameter Settings for User Entity Instance: standard_1c6:inst3|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo
 28. Parameter Settings for User Entity Instance: standard_1c6:inst3|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic
 29. Parameter Settings for User Entity Instance: delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component
 30. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 31. Multiplexer Restructuring Statistics (Restructuring Performed)
 32. Registers Protected by SYN_PRESERVE, DONT_TOUCH
 33. State Machine - |standard|standard_1c6:inst3|sdram:the_sdram|i_state
 34. State Machine - |standard|standard_1c6:inst3|sdram:the_sdram|i_next
 35. State Machine - |standard|standard_1c6:inst3|sdram:the_sdram|m_state
 36. State Machine - |standard|standard_1c6:inst3|sdram:the_sdram|m_next
 37. State Machine - |standard|standard_1c6:inst3|i2c_master:the_i2c_master|oc_i2c_master:the_oc_i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|\statemachine:c_state
 38. State Machine - |standard|standard_1c6:inst3|i2c_master:the_i2c_master|oc_i2c_master:the_oc_i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|i2c_master_bit_ctrl:u1|c_state
 39. State Machine - |standard|standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize
 40. Partition for Top-Level Resource Utilization by Entity
 41. Analysis & Synthesis Equations
 42. Multiplexer Restructuring Statistics (Restructuring Performed)
 43. Partition "sld_hub:sld_hub_inst" Resource Utilization by Entity
 44. Analysis & Synthesis Equations
 45. altmult_add Parameter Settings by Entity Instance
 46. scfifo Parameter Settings by Entity Instance
 47. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                   ;
+-----------------------------+--------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Nov 24 14:54:31 2005            ;
; Quartus II Version          ; 5.0 Build 168 06/22/2005 SP 1.04 SJ Full Version ;
; Revision Name               ; standard                                         ;
; Top-level Entity Name       ; standard                                         ;
; Family                      ; Cyclone                                          ;
; Total logic elements        ; N/A until Partition Merge                        ;
; Total pins                  ; N/A until Partition Merge                        ;
; Total virtual pins          ; N/A until Partition Merge                        ;
; Total memory bits           ; N/A until Partition Merge                        ;
; Total PLLs                  ; N/A until Partition Merge                        ;
+-----------------------------+--------------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device                                                             ; EP1C6F256C8  ;               ;
; Top-level entity name                                              ; standard     ; standard      ;
; Family name                                                        ; Cyclone      ; Stratix       ;
; Use smart compilation                                              ; On           ; Off           ;
; Remove Duplicate Logic                                             ; Off          ; On            ;
; Restructure Multiplexers                                           ; Auto         ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off          ; off           ;
; Preserve fewer node names                                          ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off          ; Off           ;
; Verilog Version                                                    ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93       ; VHDL93        ;
; State Machine Processing                                           ; Auto         ; Auto          ;
; Extract Verilog State Machines                                     ; On           ; On            ;
; Extract VHDL State Machines                                        ; On           ; On            ;
; Add Pass-Through Logic to Inferred RAMs                            ; On           ; On            ;
; NOT Gate Push-Back                                                 ; On           ; On            ;
; Power-Up Don't Care                                                ; On           ; On            ;
; Remove Redundant Logic Cells                                       ; Off          ; Off           ;
; Remove Duplicate Registers                                         ; On           ; On            ;
; Ignore CARRY Buffers                                               ; Off          ; Off           ;
; Ignore CASCADE Buffers                                             ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off          ; Off           ;
; Ignore LCELL Buffers                                               ; Off          ; Off           ;