📄 standard.pin
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.5V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. This pin can either be left unconnected or
-- connected to GND. Connecting this pin to GND will improve the
-- device's immunity to noise.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
---------------------------------------------------------------------------------
Quartus II Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version
CHIP "standard" ASSIGNED TO AN: EP1C6F256C8
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A1 : gnd : : : :
LED : A2 : output : LVTTL : : 2 : Y
VCCIO2 : A3 : power : : 3.3V : 2 :
F_nCS : A4 : output : LVTTL : : 2 : Y
GND : A5 : gnd : : : :
D[8] : A6 : bidir : LVTTL : : 2 : Y
VCCINT : A7 : power : : 1.5V : :
D[2] : A8 : bidir : LVTTL : : 2 : Y
D[3] : A9 : bidir : LVTTL : : 2 : Y
VCCINT : A10 : power : : 1.5V : :
D[12] : A11 : bidir : LVTTL : : 2 : Y
GND : A12 : gnd : : : :
D[6] : A13 : bidir : LVTTL : : 2 : Y
VCCIO2 : A14 : power : : 3.3V : 2 :
D[15] : A15 : bidir : LVTTL : : 2 : Y
GND : A16 : gnd : : : :
SDRAM_A[3] : B1 : output : LVTTL : : 1 : Y
SYS_nRST : B2 : input : LVTTL : : 2 : Y
A[0] : B3 : output : LVTTL : : 2 : Y
F_nOE : B4 : output : LVTTL : : 2 : Y
D[0] : B5 : bidir : LVTTL : : 2 : Y
D[1] : B6 : bidir : LVTTL : : 2 : Y
D[9] : B7 : bidir : LVTTL : : 2 : Y
D[10] : B8 : bidir : LVTTL : : 2 : Y
D[11] : B9 : bidir : LVTTL : : 2 : Y
D[4] : B10 : bidir : LVTTL : : 2 : Y
D[5] : B11 : bidir : LVTTL : : 2 : Y
D[13] : B12 : bidir : LVTTL : : 2 : Y
D[14] : B13 : bidir : LVTTL : : 2 : Y
D[7] : B14 : bidir : LVTTL : : 2 : Y
A[17] : B15 : output : LVTTL : : 2 : Y
P0[24] : B16 : bidir : LVTTL : : 3 : N
VCCIO1 : C1 : power : : 3.3V : 1 :
SDRAM_A[2] : C2 : output : LVTTL : : 1 : Y
SDRAM_A[1] : C3 : output : LVTTL : : 1 : Y
A[1] : C4 : output : LVTTL : : 2 : Y
A[22] : C5 : output : LVTTL : : 2 : Y
F_nWE : C6 : output : LVTTL : : 2 : Y
A[20] : C7 : output : LVTTL : : 2 : Y
A[15] : C8 : output : LVTTL : : 2 : Y
A[13] : C9 : output : LVTTL : : 2 : Y
A[11] : C10 : output : LVTTL : : 2 : Y
A[4] : C11 : output : LVTTL : : 2 : Y
A[6] : C12 : output : LVTTL : : 2 : Y
A[8] : C13 : output : LVTTL : : 2 : Y
IO_nCS3 : C14 : output : LVTTL : : 3 : Y
RESERVED_INPUT : C15 : : : : 3 :
VCCIO3 : C16 : power : : 3.3V : 3 :
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