📄 standard_1c6.ptf
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{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "3";
}
PORT chipselect
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT irq
{
Is_Enabled = "1";
direction = "output";
type = "irq";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "16";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "16";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = "Timer with 10 ms timeout period.";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
always_run = "0";
fixed_period = "0";
snapshot = "1";
period = "10";
period_units = "ms";
reset_output = "0";
timeout_pulse_output = "0";
mult = "0.001";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_clock_timer.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE high_res_timer
{
class = "altera_avalon_timer";
class_version = "2.1";
iss_model_name = "altera_avalon_timer";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "0";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "4";
}
Base_Address = "0x00280180";
}
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "3";
}
PORT chipselect
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT irq
{
Is_Enabled = "1";
direction = "output";
type = "irq";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "16";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "16";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = "Timer with 1 ms timeout period.";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
always_run = "0";
fixed_period = "0";
snapshot = "1";
period = "1";
period_units = "ms";
reset_output = "0";
timeout_pulse_output = "0";
mult = "0.001";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/high_res_timer.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE watchdog
{
class = "altera_avalon_timer";
class_version = "2.1";
iss_model_name = "altera_avalon_timer";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "0";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "5";
}
Base_Address = "0x002801A0";
}
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "3";
}
PORT chipselect
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT irq
{
Is_Enabled = "1";
direction = "output";
type = "irq";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "16";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT resetrequest
{
Is_Enabled = "1";
direction = "output";
type = "resetrequest";
width = "1";
}
PORT write_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "16";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = "Timer with 1 s timeout period.";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
always_run = "1";
fixed_period = "1";
snapshot = "0";
period = "1";
period_units = "s";
reset_output = "1";
timeout_pulse_output = "0";
mult = "1";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/watchdog.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE sdram
{
class = "altera_avalon_new_sdram_controller";
class_version = "4.2";
iss_model_name = "altera_memory";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Maximum_Pending_Read_Transactions = "7";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Is_Memory_Device = "1";
Address_Width = "22";
Data_Width = "16";
Simulation_Num_Lanes = "1";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
Base_Address = "0x01000000";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
PORT_WIRING
{
PORT zs_addr
{
direction = "output";
width = "12";
Is_Enabled = "1";
}
PORT zs_ba
{
direction = "output";
width = "2";
Is_Enabled = "1";
}
PORT zs_cas_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_cke
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_cs_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_dq
{
direction = "inout";
width = "16";
Is_Enabled = "1";
}
PORT zs_dqm
{
direction = "output";
width = "2";
Is_Enabled = "1";
}
PORT zs_ras_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_we_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT az_addr
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "22";
}
PORT az_be_n
{
Is_Enabled = "1";
direction = "input";
type = "byteenable_n";
width = "2";
}
PORT az_cs
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT az_data
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
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