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Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE uart
{
class = "altera_avalon_uart";
class_version = "4.2";
iss_model_name = "altera_avalon_uart";
PORT_WIRING
{
PORT rxd
{
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT txd
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT cts_n
{
direction = "input";
width = "1";
Is_Enabled = "0";
}
PORT rts_n
{
direction = "output";
width = "1";
Is_Enabled = "0";
}
}
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "1";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "1";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "1";
}
Base_Address = "0x00280120";
}
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "3";
}
PORT begintransfer
{
Is_Enabled = "1";
direction = "input";
type = "begintransfer";
width = "1";
}
PORT chipselect
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT dataavailable
{
Is_Enabled = "1";
direction = "output";
type = "dataavailable";
width = "1";
}
PORT irq
{
Is_Enabled = "1";
direction = "output";
type = "irq";
width = "1";
}
PORT read_n
{
Is_Enabled = "1";
direction = "input";
type = "read_n";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "16";
}
PORT readyfordata
{
Is_Enabled = "1";
direction = "output";
type = "readyfordata";
width = "1";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "16";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Iss_Launch_Telnet = "0";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = "8-bit UART with 115200 baud, <br>
1 stop bits and N parity";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = " Bus Interface";
format = "Divider";
}
SIGNAL b
{
name = "chipselect";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "writedata";
radix = "hexadecimal";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL f
{
name = " Internals";
format = "Divider";
}
SIGNAL g
{
name = "tx_ready";
}
SIGNAL h
{
name = "tx_data";
radix = "ascii";
}
SIGNAL i
{
name = "rx_char_ready";
}
SIGNAL j
{
name = "rx_data";
radix = "ascii";
}
}
INTERACTIVE_OUT log
{
enable = "0";
file = "_log_module.txt";
radix = "ascii";
signals = "temp,list";
exe = "perl -- tail-f.pl";
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "perl -- uart.pl";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
baud = "115200";
data_bits = "8";
fixed_baud = "0";
parity = "N";
stop_bits = "1";
use_cts_rts = "0";
use_eop_register = "0";
sim_true_baud = "0";
sim_char_stream = "";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart.v";
Synthesis_Only_Files = "";
}
}
MODULE spi
{
class = "altera_avalon_spi";
class_version = "2.1";
SLAVE spi_control_port
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "0";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "1";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "2";
}
Base_Address = "0x00280140";
}
PORT_WIRING
{
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT data_from_cpu
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "16";
}
PORT data_to_cpu
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "16";
}
PORT dataavailable
{
Is_Enabled = "1";
direction = "output";
type = "dataavailable";
width = "1";
}
PORT endofpacket
{
Is_Enabled = "1";
direction = "output";
type = "endofpacket";
width = "1";
}
PORT irq
{
Is_Enabled = "1";
direction = "output";
type = "irq";
width = "1";
}
PORT mem_addr
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "3";
}
PORT read_n
{
Is_Enabled = "1";
direction = "input";
type = "read_n";
width = "1";
}
PORT readyfordata
{
Is_Enabled = "1";
direction = "output";
type = "readyfordata";
width = "1";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT spi_select
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT write_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
}
PORT_WIRING
{
PORT MISO
{
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT MOSI
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT SCLK
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT SS_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
databits = "8";
targetclock = "400";
clockunits = "kHz";
clockmult = "1000";
numslaves = "1";
ismaster = "1";
clockpolarity = "1";
clockphase = "0";
lsbfirst = "0";
extradelay = "0";
targetssdelay = "100";
delayunits = "us";
delaymult = "1e-006";
clockunit = "kHz";
delayunit = "us";
prefix = "spi_";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/spi.v";
Synthesis_Only_Files = "";
}
}
MODULE sys_clock_timer
{
class = "altera_avalon_timer";
class_version = "2.1";
iss_model_name = "altera_avalon_timer";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "0";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "3";
}
Base_Address = "0x00280160";
}
PORT_WIRING
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