standard_1c6.v

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

                                       cpu_0_data_master_qualified_request_DM9000_s1,
                                       cpu_0_data_master_qualified_request_PACK_s1,
                                       cpu_0_data_master_qualified_request_S1D13503_Memory_s1,
                                       cpu_0_data_master_qualified_request_S1D13503_Register_s1,
                                       cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module,
                                       cpu_0_data_master_qualified_request_epcs_controller_epcs_control_port,
                                       cpu_0_data_master_qualified_request_ext_flash_s1,
                                       cpu_0_data_master_qualified_request_high_res_timer_s1,
                                       cpu_0_data_master_qualified_request_i2c_master_avalon_slave,
                                       cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
                                       cpu_0_data_master_qualified_request_k9f2808u0c_avalon_tristate_slave,
                                       cpu_0_data_master_qualified_request_led_s1,
                                       cpu_0_data_master_qualified_request_p0_7_p0_30_s1,
                                       cpu_0_data_master_qualified_request_p1_16_p1_25_s1,
                                       cpu_0_data_master_qualified_request_p2_16_p2_31_s1,
                                       cpu_0_data_master_qualified_request_sdram_s1,
                                       cpu_0_data_master_qualified_request_spi_spi_control_port,
                                       cpu_0_data_master_qualified_request_sys_clock_timer_s1,
                                       cpu_0_data_master_qualified_request_sysid_control_slave,
                                       cpu_0_data_master_qualified_request_uart_s1,
                                       cpu_0_data_master_qualified_request_watchdog_s1,
                                       cpu_0_data_master_read,
                                       cpu_0_data_master_read_data_valid_CF_IDE_s1,
                                       cpu_0_data_master_read_data_valid_DM9000_IRQ_s1,
                                       cpu_0_data_master_read_data_valid_DM9000_RST_s1,
                                       cpu_0_data_master_read_data_valid_DM9000_s1,
                                       cpu_0_data_master_read_data_valid_PACK_s1,
                                       cpu_0_data_master_read_data_valid_S1D13503_Memory_s1,
                                       cpu_0_data_master_read_data_valid_S1D13503_Register_s1,
                                       cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module,
                                       cpu_0_data_master_read_data_valid_epcs_controller_epcs_control_port,
                                       cpu_0_data_master_read_data_valid_ext_flash_s1,
                                       cpu_0_data_master_read_data_valid_high_res_timer_s1,
                                       cpu_0_data_master_read_data_valid_i2c_master_avalon_slave,
                                       cpu_0_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
                                       cpu_0_data_master_read_data_valid_k9f2808u0c_avalon_tristate_slave,
                                       cpu_0_data_master_read_data_valid_led_s1,
                                       cpu_0_data_master_read_data_valid_p0_7_p0_30_s1,
                                       cpu_0_data_master_read_data_valid_p1_16_p1_25_s1,
                                       cpu_0_data_master_read_data_valid_p2_16_p2_31_s1,
                                       cpu_0_data_master_read_data_valid_sdram_s1,
                                       cpu_0_data_master_read_data_valid_sdram_s1_shift_register,
                                       cpu_0_data_master_read_data_valid_spi_spi_control_port,
                                       cpu_0_data_master_read_data_valid_sys_clock_timer_s1,
                                       cpu_0_data_master_read_data_valid_sysid_control_slave,
                                       cpu_0_data_master_read_data_valid_uart_s1,
                                       cpu_0_data_master_read_data_valid_watchdog_s1,
                                       cpu_0_data_master_requests_CF_IDE_s1,
                                       cpu_0_data_master_requests_DM9000_IRQ_s1,
                                       cpu_0_data_master_requests_DM9000_RST_s1,
                                       cpu_0_data_master_requests_DM9000_s1,
                                       cpu_0_data_master_requests_PACK_s1,
                                       cpu_0_data_master_requests_S1D13503_Memory_s1,
                                       cpu_0_data_master_requests_S1D13503_Register_s1,
                                       cpu_0_data_master_requests_cpu_0_jtag_debug_module,
                                       cpu_0_data_master_requests_epcs_controller_epcs_control_port,
                                       cpu_0_data_master_requests_ext_flash_s1,
                                       cpu_0_data_master_requests_high_res_timer_s1,
                                       cpu_0_data_master_requests_i2c_master_avalon_slave,
                                       cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave,
                                       cpu_0_data_master_requests_k9f2808u0c_avalon_tristate_slave,
                                       cpu_0_data_master_requests_led_s1,
                                       cpu_0_data_master_requests_p0_7_p0_30_s1,
                                       cpu_0_data_master_requests_p1_16_p1_25_s1,
                                       cpu_0_data_master_requests_p2_16_p2_31_s1,
                                       cpu_0_data_master_requests_sdram_s1,
                                       cpu_0_data_master_requests_spi_spi_control_port,
                                       cpu_0_data_master_requests_sys_clock_timer_s1,
                                       cpu_0_data_master_requests_sysid_control_slave,
                                       cpu_0_data_master_requests_uart_s1,
                                       cpu_0_data_master_requests_watchdog_s1,
                                       cpu_0_data_master_write,
                                       cpu_0_data_master_writedata,
                                       cpu_0_jtag_debug_module_readdata_from_sa,
                                       d1_DM9000_IRQ_s1_end_xfer,
                                       d1_DM9000_RST_s1_end_xfer,
                                       d1_cpu_0_jtag_debug_module_end_xfer,
                                       d1_epcs_controller_epcs_control_port_end_xfer,
                                       d1_ext_mem_bus_avalon_slave_end_xfer,
                                       d1_high_res_timer_s1_end_xfer,
                                       d1_i2c_master_avalon_slave_end_xfer,
                                       d1_jtag_uart_avalon_jtag_slave_end_xfer,
                                       d1_led_s1_end_xfer,
                                       d1_nand_flash_bus_avalon_slave_end_xfer,
                                       d1_p0_7_p0_30_s1_end_xfer,
                                       d1_p1_16_p1_25_s1_end_xfer,
                                       d1_p2_16_p2_31_s1_end_xfer,
                                       d1_sdram_s1_end_xfer,
                                       d1_spi_spi_control_port_end_xfer,
                                       d1_sys_clock_timer_s1_end_xfer,
                                       d1_sysid_control_slave_end_xfer,
                                       d1_uart_s1_end_xfer,
                                       d1_watchdog_s1_end_xfer,
                                       epcs_controller_epcs_control_port_irq_from_sa,
                                       epcs_controller_epcs_control_port_readdata_from_sa,
                                       ext_flash_s1_wait_counter_eq_0,
                                       ext_flash_s1_wait_counter_eq_1,
                                       high_res_timer_s1_irq_from_sa,
                                       high_res_timer_s1_readdata_from_sa,
                                       i2c_master_avalon_slave_irq_from_sa,
                                       i2c_master_avalon_slave_readdata_from_sa,
                                       i2c_master_avalon_slave_waitrequest_n_from_sa,
                                       incoming_ext_mem_bus_data,
                                       incoming_ext_mem_bus_data_with_Xs_converted_to_0,
                                       incoming_nand_flash_bus_data,
                                       jtag_uart_avalon_jtag_slave_irq_from_sa,
                                       jtag_uart_avalon_jtag_slave_readdata_from_sa,
                                       jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
                                       k9f2808u0c_avalon_tristate_slave_wait_counter_eq_0,
                                       k9f2808u0c_avalon_tristate_slave_wait_counter_eq_1,
                                       p0_7_p0_30_s1_irq_from_sa,
                                       p0_7_p0_30_s1_readdata_from_sa,
                                       p1_16_p1_25_s1_irq_from_sa,
                                       p1_16_p1_25_s1_readdata_from_sa,
                                       p2_16_p2_31_s1_irq_from_sa,
                                       p2_16_p2_31_s1_readdata_from_sa,
                                       registered_cpu_0_data_master_read_data_valid_CF_IDE_s1,
                                       registered_cpu_0_data_master_read_data_valid_DM9000_s1,
                                       registered_cpu_0_data_master_read_data_valid_PACK_s1,
                                       registered_cpu_0_data_master_read_data_valid_S1D13503_Memory_s1,
                                       registered_cpu_0_data_master_read_data_valid_S1D13503_Register_s1,
                                       registered_cpu_0_data_master_read_data_valid_ext_flash_s1,
                                       registered_cpu_0_data_master_read_data_valid_k9f2808u0c_avalon_tristate_slave,
                                       reset_n,
                                       sdram_s1_posted_fifo_readenable,
                                       sdram_s1_posted_fifo_writenable,
                                       sdram_s1_readdata_from_sa,
                                       sdram_s1_waitrequest_from_sa,
                                       spi_spi_control_port_irq_from_sa,
                                       spi_spi_control_port_readdata_from_sa,
                                       sys_clock_timer_s1_irq_from_sa,
                                       sys_clock_timer_s1_readdata_from_sa,
                                       sysid_control_slave_readdata_from_sa,
                                       uart_s1_irq_from_sa,
                                       uart_s1_readdata_from_sa,
                                       watchdog_s1_irq_from_sa,
                                       watchdog_s1_readdata_from_sa,

                                      // outputs:
                                       cpu_0_data_master_address_to_slave,
                                       cpu_0_data_master_dbs_address,
                                       cpu_0_data_master_dbs_write_16,
                                       cpu_0_data_master_irq,
                                       cpu_0_data_master_no_byte_enables_and_last_term,
                                       cpu_0_data_master_readdata,
                                       cpu_0_data_master_waitrequest
                                    );

  output  [ 26: 0] cpu_0_data_master_address_to_slave;
  output  [  1: 0] cpu_0_data_master_dbs_address;
  output  [ 15: 0] cpu_0_data_master_dbs_write_16;
  output  [ 31: 0] cpu_0_data_master_irq;
  output           cpu_0_data_master_no_byte_enables_and_last_term;
  output  [ 31: 0] cpu_0_data_master_readdata;
  output           cpu_0_data_master_waitrequest;
  input            CF_IDE_s1_wait_counter_eq_0;
  input            CF_IDE_s1_wait_counter_eq_1;
  input            DM9000_IRQ_s1_irq_from_sa;
  input            DM9000_IRQ_s1_readdata_from_sa;
  input            DM9000_s1_wait_counter_eq_0;
  input            DM9000_s1_wait_counter_eq_1;
  input            PACK_s1_wait_counter_eq_0;
  input            PACK_s1_wait_counter_eq_1;
  input            S1D13503_Memory_s1_wait_counter_eq_0;
  input            S1D13503_Memory_s1_wait_counter_eq_1;
  input            S1D13503_Register_s1_wait_counter_eq_0;
  input            S1D13503_Register_s1_wait_counter_eq_1;
  input            clk;
  input   [ 26: 0] cpu_0_data_master_address;
  input   [  1: 0] cpu_0_data_master_byteenable_ext_flash_s1;
  input   [  1: 0] cpu_0_data_master_byteenable_sdram_s1;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_granted_CF_IDE_s1;
  input            cpu_0_data_master_granted_DM9000_IRQ_s1;
  input            cpu_0_data_master_granted_DM9000_RST_s1;
  input            cpu_0_data_master_granted_DM9000_s1;
  input            cpu_0_data_master_granted_PACK_s1;
  input            cpu_0_data_master_granted_S1D13503_Memory_s1;
  input            cpu_0_data_master_granted_S1D13503_Register_s1;
  input            cpu_0_data_master_granted_cpu_0_jtag_debug_module;
  input            cpu_0_data_master_granted_epcs_controller_epcs_control_port;
  input            cpu_0_data_master_granted_ext_flash_s1;
  input            cpu_0_data_master_granted_high_res_timer_s1;
  input            cpu_0_data_master_granted_i2c_master_avalon_slave;
  input            cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave;
  input            cpu_0_data_master_granted_k9f2808u0c_avalon_tristate_slave;
  input            cpu_0_data_master_granted_led_s1;
  input            cpu_0_data_master_granted_p0_7_p0_30_s1;
  input            cpu_0_data_master_granted_p1_16_p1_25_s1;
  input            cpu_0_data_master_granted_p2_16_p2_31_s1;
  input            cpu_0_data_master_granted_sdram_s1;
  input            cpu_0_data_master_granted_spi_spi_control_port;
  input            cpu_0_data_master_granted_sys_clock_timer_s1;
  input            cpu_0_data_master_granted_sysid_control_slave;
  input            cpu_0_data_master_granted_uart_s1;
  input            cpu_0_data_master_granted_watchdog_s1;
  input            cpu_0_data_master_qualified_request_CF_IDE_s1;
  input            cpu_0_data_master_qualified_request_DM9000_IRQ_s1;
  input            cpu_0_data_master_qualified_request_DM9000_RST_s1;
  input            cpu_0_data_master_qualified_request_DM9000_s1;
  input            cpu_0_data_master_qualified_request_PACK_s1;
  input            cpu_0_data_master_qualified_request_S1D13503_Memory_s1;
  input            cpu_0_data_master_qualified_request_S1D13503_Register_s1;
  input            cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
  input            cpu_0_data_master_qualified_request_epcs_controller_epcs_control_port;
  input            cpu_0_data_master_qualified_request_ext_flash_s1;
  input            cpu_0_data_master_qualified_request_high_res_timer_s1;
  input            cpu_0_data_master_qualified_request_i2c_master_avalon_slave;
  input            cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  input            cpu_0_data_master_qualified_request_k9f2808u0c_avalon_tristate_slave;
  input            cpu_0_data_master_qualified_request_led_s1;
  input            cpu_0_data_master_qualified_request_p0_7_p0_30_s1;
  input            cpu_0_data_master_qualified_request_p1_16_p1_25_s1;
  input            cpu_0_data_master_qualified_request_p2_16_p2_31_s1;
  input            cpu_0_data_master_qualified_request_sdram_s1;