standard_1c6.v

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0


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// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module DM9000_IRQ_s1_arbitrator (
                                  // inputs:
                                   DM9000_IRQ_s1_irq,
                                   DM9000_IRQ_s1_readdata,
                                   clk,
                                   cpu_0_data_master_address_to_slave,
                                   cpu_0_data_master_read,
                                   cpu_0_data_master_waitrequest,
                                   cpu_0_data_master_write,
                                   cpu_0_data_master_writedata,
                                   reset_n,

                                  // outputs:
                                   DM9000_IRQ_s1_address,
                                   DM9000_IRQ_s1_chipselect,
                                   DM9000_IRQ_s1_irq_from_sa,
                                   DM9000_IRQ_s1_readdata_from_sa,
                                   DM9000_IRQ_s1_reset_n,
                                   DM9000_IRQ_s1_write_n,
                                   DM9000_IRQ_s1_writedata,
                                   cpu_0_data_master_granted_DM9000_IRQ_s1,
                                   cpu_0_data_master_qualified_request_DM9000_IRQ_s1,
                                   cpu_0_data_master_read_data_valid_DM9000_IRQ_s1,
                                   cpu_0_data_master_requests_DM9000_IRQ_s1,
                                   d1_DM9000_IRQ_s1_end_xfer
                                );

  output  [  1: 0] DM9000_IRQ_s1_address;
  output           DM9000_IRQ_s1_chipselect;
  output           DM9000_IRQ_s1_irq_from_sa;
  output           DM9000_IRQ_s1_readdata_from_sa;
  output           DM9000_IRQ_s1_reset_n;
  output           DM9000_IRQ_s1_write_n;
  output           DM9000_IRQ_s1_writedata;
  output           cpu_0_data_master_granted_DM9000_IRQ_s1;
  output           cpu_0_data_master_qualified_request_DM9000_IRQ_s1;
  output           cpu_0_data_master_read_data_valid_DM9000_IRQ_s1;
  output           cpu_0_data_master_requests_DM9000_IRQ_s1;
  output           d1_DM9000_IRQ_s1_end_xfer;
  input            DM9000_IRQ_s1_irq;
  input            DM9000_IRQ_s1_readdata;
  input            clk;
  input   [ 26: 0] cpu_0_data_master_address_to_slave;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_waitrequest;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] DM9000_IRQ_s1_address;
  wire             DM9000_IRQ_s1_allgrants;
  wire             DM9000_IRQ_s1_allow_new_arb_cycle;
  wire             DM9000_IRQ_s1_any_continuerequest;
  wire             DM9000_IRQ_s1_arb_counter_enable;
  reg     [  1: 0] DM9000_IRQ_s1_arb_share_counter;
  wire    [  1: 0] DM9000_IRQ_s1_arb_share_counter_next_value;
  wire    [  1: 0] DM9000_IRQ_s1_arb_share_set_values;
  wire             DM9000_IRQ_s1_arbitration_holdoff_internal;
  wire             DM9000_IRQ_s1_beginbursttransfer_internal;
  wire             DM9000_IRQ_s1_begins_xfer;
  wire             DM9000_IRQ_s1_chipselect;
  wire             DM9000_IRQ_s1_end_xfer;
  wire             DM9000_IRQ_s1_firsttransfer;
  wire             DM9000_IRQ_s1_grant_vector;
  wire             DM9000_IRQ_s1_in_a_read_cycle;
  wire             DM9000_IRQ_s1_in_a_write_cycle;
  wire             DM9000_IRQ_s1_irq_from_sa;
  wire             DM9000_IRQ_s1_master_qreq_vector;
  wire             DM9000_IRQ_s1_readdata_from_sa;
  wire             DM9000_IRQ_s1_reset_n;
  reg              DM9000_IRQ_s1_slavearbiterlockenable;
  wire             DM9000_IRQ_s1_waits_for_read;
  wire             DM9000_IRQ_s1_waits_for_write;
  wire             DM9000_IRQ_s1_write_n;
  wire             DM9000_IRQ_s1_writedata;
  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_DM9000_IRQ_s1;
  wire             cpu_0_data_master_qualified_request_DM9000_IRQ_s1;
  wire             cpu_0_data_master_read_data_valid_DM9000_IRQ_s1;
  wire             cpu_0_data_master_requests_DM9000_IRQ_s1;
  wire             cpu_0_data_master_saved_grant_DM9000_IRQ_s1;
  reg              d1_DM9000_IRQ_s1_end_xfer;
  reg              d1_reasons_to_wait;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             wait_for_DM9000_IRQ_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~DM9000_IRQ_s1_end_xfer;
    end


  assign DM9000_IRQ_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_DM9000_IRQ_s1));
  //assign DM9000_IRQ_s1_readdata_from_sa = DM9000_IRQ_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign DM9000_IRQ_s1_readdata_from_sa = DM9000_IRQ_s1_readdata;

  assign cpu_0_data_master_requests_DM9000_IRQ_s1 = ({cpu_0_data_master_address_to_slave[26 : 4] , 4'b0} == 27'h280210) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //DM9000_IRQ_s1_arb_share_counter set values, which is an e_mux
  assign DM9000_IRQ_s1_arb_share_set_values = 1;

  //DM9000_IRQ_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign DM9000_IRQ_s1_arb_share_counter_next_value = DM9000_IRQ_s1_firsttransfer ? (DM9000_IRQ_s1_arb_share_set_values - 1) : |DM9000_IRQ_s1_arb_share_counter ? (DM9000_IRQ_s1_arb_share_counter - 1) : 0;

  //DM9000_IRQ_s1_allgrants all slave grants, which is an e_mux
  assign DM9000_IRQ_s1_allgrants = |DM9000_IRQ_s1_grant_vector;

  //DM9000_IRQ_s1_end_xfer assignment, which is an e_assign
  assign DM9000_IRQ_s1_end_xfer = ~(DM9000_IRQ_s1_waits_for_read | DM9000_IRQ_s1_waits_for_write);

  //DM9000_IRQ_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign DM9000_IRQ_s1_arb_counter_enable = DM9000_IRQ_s1_end_xfer & DM9000_IRQ_s1_allgrants;

  //DM9000_IRQ_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          DM9000_IRQ_s1_arb_share_counter <= 0;
      else if (DM9000_IRQ_s1_arb_counter_enable)
          DM9000_IRQ_s1_arb_share_counter <= DM9000_IRQ_s1_arb_share_counter_next_value;
    end


  //DM9000_IRQ_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          DM9000_IRQ_s1_slavearbiterlockenable <= 0;
      else if (|DM9000_IRQ_s1_master_qreq_vector & DM9000_IRQ_s1_end_xfer)
          DM9000_IRQ_s1_slavearbiterlockenable <= |DM9000_IRQ_s1_arb_share_counter_next_value;
    end


  //cpu_0/data_master DM9000_IRQ/s1 arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = DM9000_IRQ_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //DM9000_IRQ_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign DM9000_IRQ_s1_any_continuerequest = 0;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 0;

  assign cpu_0_data_master_qualified_request_DM9000_IRQ_s1 = cpu_0_data_master_requests_DM9000_IRQ_s1 & ~(((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
  //DM9000_IRQ_s1_writedata mux, which is an e_mux
  assign DM9000_IRQ_s1_writedata = cpu_0_data_master_writedata;

  //master is always granted when requested
  assign cpu_0_data_master_granted_DM9000_IRQ_s1 = cpu_0_data_master_qualified_request_DM9000_IRQ_s1;

  //cpu_0/data_master saved-grant DM9000_IRQ/s1, which is an e_assign
  assign cpu_0_data_master_saved_grant_DM9000_IRQ_s1 = cpu_0_data_master_requests_DM9000_IRQ_s1;

  //allow new arb cycle for DM9000_IRQ/s1, which is an e_assign
  assign DM9000_IRQ_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign DM9000_IRQ_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign DM9000_IRQ_s1_master_qreq_vector = 1;

  //DM9000_IRQ_s1_reset_n assignment, which is an e_assign
  assign DM9000_IRQ_s1_reset_n = reset_n;

  assign DM9000_IRQ_s1_chipselect = cpu_0_data_master_granted_DM9000_IRQ_s1;
  //DM9000_IRQ_s1_firsttransfer first transaction, which is an e_assign
  assign DM9000_IRQ_s1_firsttransfer = ~(DM9000_IRQ_s1_slavearbiterlockenable & DM9000_IRQ_s1_any_continuerequest);

  //DM9000_IRQ_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign DM9000_IRQ_s1_beginbursttransfer_internal = DM9000_IRQ_s1_begins_xfer & DM9000_IRQ_s1_firsttransfer;

  //DM9000_IRQ_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign DM9000_IRQ_s1_arbitration_holdoff_internal = DM9000_IRQ_s1_begins_xfer & DM9000_IRQ_s1_firsttransfer;

  //~DM9000_IRQ_s1_write_n assignment, which is an e_mux
  assign DM9000_IRQ_s1_write_n = ~(cpu_0_data_master_granted_DM9000_IRQ_s1 & cpu_0_data_master_write);

  //DM9000_IRQ_s1_address mux, which is an e_mux
  assign DM9000_IRQ_s1_address = cpu_0_data_master_address_to_slave >> 2;

  //d1_DM9000_IRQ_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_DM9000_IRQ_s1_end_xfer <= 1;
      else if (1)
          d1_DM9000_IRQ_s1_end_xfer <= DM9000_IRQ_s1_end_xfer;
    end


  //DM9000_IRQ_s1_waits_for_read in a cycle, which is an e_mux
  assign DM9000_IRQ_s1_waits_for_read = DM9000_IRQ_s1_in_a_read_cycle & DM9000_IRQ_s1_begins_xfer;

  //DM9000_IRQ_s1_in_a_read_cycle assignment, which is an e_assign
  assign DM9000_IRQ_s1_in_a_read_cycle = cpu_0_data_master_granted_DM9000_IRQ_s1 & cpu_0_data_master_read;