standard.tan.rpt

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; fmax Requirement                                      ; 55.0 MHz           ;      ;    ;             ;
; Ignore Clock Settings                                 ; On                 ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                            ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                           ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; PLL:inst|altpll:altpll_component|_clk0    ;                    ; PLL output ; 48.0 MHz         ; 0.000 ns      ; 0.000 ns     ; SYS_CLK  ; 1                     ; 1                   ; -1.885 ns ;              ;
; PLL:inst|altpll:altpll_component|_extclk0 ;                    ; PLL output ; 48.0 MHz         ; 0.000 ns      ; 0.000 ns     ; SYS_CLK  ; 1                     ; 1                   ; -1.885 ns ;              ;
; SYS_CLK                                   ;                    ; User Pin   ; 48.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP              ;                    ; User Pin   ; 55.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~UPDATEUSER           ;                    ; User Pin   ; 55.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A       ;              ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'PLL:inst|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                          ; To                                                                                                                  ; From Clock                             ; To Clock                               ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+-----------------------------+---------------------------+-------------------------+
; 1.127 ns                                ; 50.75 MHz ( period = 19.706 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|d_write                                                                                                    ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[3]          ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.800 ns                 ; 18.673 ns               ;
; 1.156 ns                                ; 50.82 MHz ( period = 19.677 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|d_write                                                                                                    ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[17]         ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.800 ns                 ; 18.644 ns               ;
; 1.193 ns                                ; 50.92 MHz ( period = 19.640 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|d_write                                                                                                    ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[8]          ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.800 ns                 ; 18.607 ns               ;
; 1.209 ns                                ; 50.96 MHz ( period = 19.624 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|d_write                                                                                                    ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[23]         ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.800 ns                 ; 18.591 ns               ;
; 1.249 ns                                ; 51.06 MHz ( period = 19.584 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|d_write                                                                                                    ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[6]          ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.800 ns                 ; 18.551 ns               ;
; 1.307 ns                                ; 51.21 MHz ( period = 19.526 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|ic_fill_tag[11]                                                                                            ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[3]          ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.803 ns                 ; 18.496 ns               ;
; 1.321 ns                                ; 51.25 MHz ( period = 19.512 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|d_write                                                                                                    ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[4]          ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.800 ns                 ; 18.479 ns               ;
; 1.336 ns                                ; 51.29 MHz ( period = 19.497 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|ic_fill_tag[11]                                                                                            ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[17]         ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.803 ns                 ; 18.467 ns               ;
; 1.336 ns                                ; 51.29 MHz ( period = 19.497 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|d_write                                                                                                    ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[5]          ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.800 ns                 ; 18.464 ns               ;
; 1.338 ns                                ; 51.30 MHz ( period = 19.495 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|d_read                                                                                                     ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[3]          ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.800 ns                 ; 18.462 ns               ;