pipemult.tan.rpt

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                            ;
+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                                                                                                      ; To                                                                                                                                                                    ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 4.466 ns                         ; rdaddress1[2]                                                                                             ; ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|ram_block1a15~portb_address_reg2                                                             ;            ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 9.761 ns                         ; ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|ram_block1a15~portb_address_reg4 ; q[9]                                                                                                                                                                  ; clk        ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.734 ns                        ; datab[3]                                                                                                  ; mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|decoder_node[3][2]                                                                                           ;            ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 197.01 MHz ( period = 5.076 ns ) ; mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|decoder_node[6][3]                               ; mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node[9] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                                           ;                                                                                                                                                                       ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6F256C6        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+