pipemult.hif

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1615
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
pipemult
# case_insensitive
# source_file
pipemult.bdf
1112597680
23
# storage
db|pipemult.(0).cnf
db|pipemult.(0).cnf
# hierarchies {
|
}
# end
# entity
ram
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ram.v
1112597682
7
# storage
db|pipemult.(1).cnf
db|pipemult.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
ram:inst1
}
# end
# entity
mult
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
mult.v
1112597676
7
# storage
db|pipemult.(4).cnf
db|pipemult.(4).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mult:inst
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|pipemult.(2).cnf
db|pipemult.(2).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_DEC
USR
WIDTHAD_A
5
PARAMETER_DEC
USR
NUMWORDS_A
32
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
16
PARAMETER_DEC
USR
WIDTHAD_B
5
PARAMETER_DEC
USR
NUMWORDS_B
32
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_j6b1
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
clock0
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
ram:inst1|altsyncram:altsyncram_component
}
# end
# entity
lpm_mult
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|lpm_mult.tdf
1114012452
6
# storage
db|pipemult.(5).cnf
db|pipemult.(5).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTHA
8
PARAMETER_DEC
USR
LPM_WIDTHB
8
PARAMETER_DEC
USR
LPM_WIDTHP
16
PARAMETER_DEC
USR
LPM_WIDTHR
0
PARAMETER_UNKNOWN
DEF
LPM_WIDTHS
16
PARAMETER_DEC
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
2
PARAMETER_DEC
USR
LATENCY
0
PARAMETER_UNKNOWN
DEF
INPUT_A_IS_CONSTANT
NO
PARAMETER_UNKNOWN
DEF
INPUT_B_IS_CONSTANT
NO
PARAMETER_UNKNOWN
DEF
USE_EAB
OFF
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
1
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
APEX20K_TECHNOLOGY_MAPPER
Lut
TECH_MAPPER_APEX20K
USR
DEDICATED_MULTIPLIER_CIRCUITRY
AUTO
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO
0
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
INPUT_A_FIXED_VALUE
Bx
PARAMETER_UNKNOWN
DEF
INPUT_B_FIXED_VALUE
Bx
PARAMETER_UNKNOWN
DEF
}
# used_port {
clock
dataa
dataa
dataa
dataa
dataa
dataa
dataa
dataa
datab
datab
datab
datab
datab
datab
datab
datab
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
c:|altera|quartus50|libraries|megafunctions|lpm_add_sub.inc
1107574408
c:|altera|quartus50|libraries|megafunctions|multcore.inc
1107575210
c:|altera|quartus50|libraries|megafunctions|bypassff.inc
1107573920
c:|altera|quartus50|libraries|megafunctions|altshift.inc
1107573438
}
# hierarchies {
mult:inst|lpm_mult:lpm_mult_component
}
# end
# entity
multcore
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|multcore.tdf
1114012452
6
# storage
db|pipemult.(6).cnf
db|pipemult.(6).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
widtha
8
PARAMETER_UNKNOWN
USR
widthb
8
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LATENCY
2
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
USE_EAB
OFF
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
6
PARAMETER_UNKNOWN
USR
OP_MODE
0
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEDICATED_MULTIPLIER_CIRCUITRY
YES
PARAMETER_UNKNOWN
DEF
SUB_DEDICATED_MULTIPLIER_CIRCUITRY
NO
PARAMETER_UNKNOWN
USR
DSP_BLOCK_BALANCING
Auto
DSP_BLOCK_BALANCING_IMPLEMENTATION
USR
}
# used_port {
dataa0
dataa1
dataa2
dataa3
dataa4
dataa5
dataa6
dataa7
datab0
datab1
datab2
datab3
datab4
datab5
datab6
datab7
clock
result0
result1
result2
result3
result4
result5
result6
result7
result8
result9
result10
result11
result12
result13
result14
result15
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
c:|altera|quartus50|libraries|megafunctions|lpm_add_sub.inc
1107574408
c:|altera|quartus50|libraries|megafunctions|csa_add.inc
1107574010
c:|altera|quartus50|libraries|megafunctions|mpar_add.inc
1107575144
c:|altera|quartus50|libraries|megafunctions|muleabz.inc
1107575194
c:|altera|quartus50|libraries|megafunctions|mul_lfrg.inc
1107575178
c:|altera|quartus50|libraries|megafunctions|mul_boothc.inc
1107575160
c:|altera|quartus50|libraries|megafunctions|alt_ded_mult_y.inc
1107572466
c:|altera|quartus50|libraries|megafunctions|alt_ded_mult.inc
1107572450
c:|altera|quartus50|libraries|megafunctions|dffpipe.inc
1107574172
}
# hierarchies {
mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core
}
# end
# entity
mpar_add
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|mpar_add.tdf
1114012454
6
# storage
db|pipemult.(7).cnf
db|pipemult.(7).cnf
# user_parameter {
size
9
PARAMETER_UNKNOWN
USR
width
8
PARAMETER_UNKNOWN
USR
REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LEVEL
1
PARAMETER_UNKNOWN
USR
TOT_LEVELS
4
PARAMETER_UNKNOWN
USR
STAGE
1
PARAMETER_UNKNOWN
USR
TOT_STAGES
4
PARAMETER_UNKNOWN
USR
INT_LATENCY
2
PARAMETER_UNKNOWN
USR
PREV_SING_SIZE
8
PARAMETER_UNKNOWN
DEF
BOOTH_ADDER
NO
PARAMETER_UNKNOWN
DEF
CREATE_MS_BOOTH_ADDER
NO
PARAMETER_UNKNOWN
DEF
MPARADD_OP_MODE
0
PARAMETER_UNKNOWN
DEF
}
# used_port {
data0_0
data0_1
data0_2
data0_3
data0_4
data0_5
data0_6
data0_7
data1_0
data1_1
data1_2
data1_3
data1_4
data1_5
data1_6
data1_7
data2_0
data2_1
data2_2
data2_3
data2_4
data2_5
data2_6
data2_7
data3_0
data3_1
data3_2
data3_3
data3_4
data3_5
data3_6
data3_7
data4_0
data4_1
data4_2
data4_3
data4_4
data4_5
data4_6
data4_7
data5_0
data5_1
data5_2
data5_3
data5_4
data5_5
data5_6
data5_7
data6_0
data6_1
data6_2
data6_3
data6_4
data6_5
data6_6
data6_7
data7_0
data7_1
data7_2
data7_3
data7_4
data7_5
data7_6
data7_7
clk
aclr
result0
result1
result2
result3
result4
result5
result6
result7
result8
result9
result10
result11
result12
result13
result14
result15
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|lpm_add_sub.inc
1107574408
c:|altera|quartus50|libraries|megafunctions|mpar_add.inc
1107575144
}
# hierarchies {
mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder
}
# end
# entity
lpm_add_sub
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|lpm_add_sub.tdf
1114012446
6
# storage
db|pipemult.(8).cnf
db|pipemult.(8).cnf
# user_parameter {
LPM_WIDTH
9
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
6
PARAMETER_UNKNOWN