pipemult.map.eqn

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

M1_q_b[6]_PORT_B_address_reg = DFFE(M1_q_b[6]_PORT_B_address, M1_q_b[6]_clock_1, , , );
M1_q_b[6]_PORT_A_write_enable = VCC;
M1_q_b[6]_PORT_A_write_enable_reg = DFFE(M1_q_b[6]_PORT_A_write_enable, M1_q_b[6]_clock_0, , , M1_q_b[6]_clock_enable_0);
M1_q_b[6]_PORT_B_read_enable = VCC;
M1_q_b[6]_PORT_B_read_enable_reg = DFFE(M1_q_b[6]_PORT_B_read_enable, M1_q_b[6]_clock_1, , , );
M1_q_b[6]_clock_0 = clk;
M1_q_b[6]_clock_1 = clk;
M1_q_b[6]_clock_enable_0 = wren1;
M1_q_b[6]_PORT_B_data_out = MEMORY(M1_q_b[6]_PORT_A_data_in_reg, , M1_q_b[6]_PORT_A_address_reg, M1_q_b[6]_PORT_B_address_reg, M1_q_b[6]_PORT_A_write_enable_reg, M1_q_b[6]_PORT_B_read_enable_reg, , , M1_q_b[6]_clock_0, M1_q_b[6]_clock_1, M1_q_b[6]_clock_enable_0, , , );
M1_q_b[6] = M1_q_b[6]_PORT_B_data_out[0];


--M1_q_b[5] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[5]_PORT_A_data_in = K12L02;
M1_q_b[5]_PORT_A_data_in_reg = DFFE(M1_q_b[5]_PORT_A_data_in, M1_q_b[5]_clock_0, , , M1_q_b[5]_clock_enable_0);
M1_q_b[5]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[5]_PORT_A_address_reg = DFFE(M1_q_b[5]_PORT_A_address, M1_q_b[5]_clock_0, , , M1_q_b[5]_clock_enable_0);
M1_q_b[5]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[5]_PORT_B_address_reg = DFFE(M1_q_b[5]_PORT_B_address, M1_q_b[5]_clock_1, , , );
M1_q_b[5]_PORT_A_write_enable = VCC;
M1_q_b[5]_PORT_A_write_enable_reg = DFFE(M1_q_b[5]_PORT_A_write_enable, M1_q_b[5]_clock_0, , , M1_q_b[5]_clock_enable_0);
M1_q_b[5]_PORT_B_read_enable = VCC;
M1_q_b[5]_PORT_B_read_enable_reg = DFFE(M1_q_b[5]_PORT_B_read_enable, M1_q_b[5]_clock_1, , , );
M1_q_b[5]_clock_0 = clk;
M1_q_b[5]_clock_1 = clk;
M1_q_b[5]_clock_enable_0 = wren1;
M1_q_b[5]_PORT_B_data_out = MEMORY(M1_q_b[5]_PORT_A_data_in_reg, , M1_q_b[5]_PORT_A_address_reg, M1_q_b[5]_PORT_B_address_reg, M1_q_b[5]_PORT_A_write_enable_reg, M1_q_b[5]_PORT_B_read_enable_reg, , , M1_q_b[5]_clock_0, M1_q_b[5]_clock_1, M1_q_b[5]_clock_enable_0, , , );
M1_q_b[5] = M1_q_b[5]_PORT_B_data_out[0];


--M1_q_b[4] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[4]_PORT_A_data_in = K12L22;
M1_q_b[4]_PORT_A_data_in_reg = DFFE(M1_q_b[4]_PORT_A_data_in, M1_q_b[4]_clock_0, , , M1_q_b[4]_clock_enable_0);
M1_q_b[4]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[4]_PORT_A_address_reg = DFFE(M1_q_b[4]_PORT_A_address, M1_q_b[4]_clock_0, , , M1_q_b[4]_clock_enable_0);
M1_q_b[4]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[4]_PORT_B_address_reg = DFFE(M1_q_b[4]_PORT_B_address, M1_q_b[4]_clock_1, , , );
M1_q_b[4]_PORT_A_write_enable = VCC;
M1_q_b[4]_PORT_A_write_enable_reg = DFFE(M1_q_b[4]_PORT_A_write_enable, M1_q_b[4]_clock_0, , , M1_q_b[4]_clock_enable_0);
M1_q_b[4]_PORT_B_read_enable = VCC;
M1_q_b[4]_PORT_B_read_enable_reg = DFFE(M1_q_b[4]_PORT_B_read_enable, M1_q_b[4]_clock_1, , , );
M1_q_b[4]_clock_0 = clk;
M1_q_b[4]_clock_1 = clk;
M1_q_b[4]_clock_enable_0 = wren1;
M1_q_b[4]_PORT_B_data_out = MEMORY(M1_q_b[4]_PORT_A_data_in_reg, , M1_q_b[4]_PORT_A_address_reg, M1_q_b[4]_PORT_B_address_reg, M1_q_b[4]_PORT_A_write_enable_reg, M1_q_b[4]_PORT_B_read_enable_reg, , , M1_q_b[4]_clock_0, M1_q_b[4]_clock_1, M1_q_b[4]_clock_enable_0, , , );
M1_q_b[4] = M1_q_b[4]_PORT_B_data_out[0];


--M1_q_b[3] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[3]_PORT_A_data_in = K51_sout_node[1];
M1_q_b[3]_PORT_A_data_in_reg = DFFE(M1_q_b[3]_PORT_A_data_in, M1_q_b[3]_clock_0, , , M1_q_b[3]_clock_enable_0);
M1_q_b[3]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[3]_PORT_A_address_reg = DFFE(M1_q_b[3]_PORT_A_address, M1_q_b[3]_clock_0, , , M1_q_b[3]_clock_enable_0);
M1_q_b[3]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[3]_PORT_B_address_reg = DFFE(M1_q_b[3]_PORT_B_address, M1_q_b[3]_clock_1, , , );
M1_q_b[3]_PORT_A_write_enable = VCC;
M1_q_b[3]_PORT_A_write_enable_reg = DFFE(M1_q_b[3]_PORT_A_write_enable, M1_q_b[3]_clock_0, , , M1_q_b[3]_clock_enable_0);
M1_q_b[3]_PORT_B_read_enable = VCC;
M1_q_b[3]_PORT_B_read_enable_reg = DFFE(M1_q_b[3]_PORT_B_read_enable, M1_q_b[3]_clock_1, , , );
M1_q_b[3]_clock_0 = clk;
M1_q_b[3]_clock_1 = clk;
M1_q_b[3]_clock_enable_0 = wren1;
M1_q_b[3]_PORT_B_data_out = MEMORY(M1_q_b[3]_PORT_A_data_in_reg, , M1_q_b[3]_PORT_A_address_reg, M1_q_b[3]_PORT_B_address_reg, M1_q_b[3]_PORT_A_write_enable_reg, M1_q_b[3]_PORT_B_read_enable_reg, , , M1_q_b[3]_clock_0, M1_q_b[3]_clock_1, M1_q_b[3]_clock_enable_0, , , );
M1_q_b[3] = M1_q_b[3]_PORT_B_data_out[0];


--M1_q_b[2] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[2]_PORT_A_data_in = K51_sout_node[0];
M1_q_b[2]_PORT_A_data_in_reg = DFFE(M1_q_b[2]_PORT_A_data_in, M1_q_b[2]_clock_0, , , M1_q_b[2]_clock_enable_0);
M1_q_b[2]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[2]_PORT_A_address_reg = DFFE(M1_q_b[2]_PORT_A_address, M1_q_b[2]_clock_0, , , M1_q_b[2]_clock_enable_0);
M1_q_b[2]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[2]_PORT_B_address_reg = DFFE(M1_q_b[2]_PORT_B_address, M1_q_b[2]_clock_1, , , );
M1_q_b[2]_PORT_A_write_enable = VCC;
M1_q_b[2]_PORT_A_write_enable_reg = DFFE(M1_q_b[2]_PORT_A_write_enable, M1_q_b[2]_clock_0, , , M1_q_b[2]_clock_enable_0);
M1_q_b[2]_PORT_B_read_enable = VCC;
M1_q_b[2]_PORT_B_read_enable_reg = DFFE(M1_q_b[2]_PORT_B_read_enable, M1_q_b[2]_clock_1, , , );
M1_q_b[2]_clock_0 = clk;
M1_q_b[2]_clock_1 = clk;
M1_q_b[2]_clock_enable_0 = wren1;
M1_q_b[2]_PORT_B_data_out = MEMORY(M1_q_b[2]_PORT_A_data_in_reg, , M1_q_b[2]_PORT_A_address_reg, M1_q_b[2]_PORT_B_address_reg, M1_q_b[2]_PORT_A_write_enable_reg, M1_q_b[2]_PORT_B_read_enable_reg, , , M1_q_b[2]_clock_0, M1_q_b[2]_clock_1, M1_q_b[2]_clock_enable_0, , , );
M1_q_b[2] = M1_q_b[2]_PORT_B_data_out[0];


--M1_q_b[1] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[1]_PORT_A_data_in = G2_drop_bits_node[0][1];
M1_q_b[1]_PORT_A_data_in_reg = DFFE(M1_q_b[1]_PORT_A_data_in, M1_q_b[1]_clock_0, , , M1_q_b[1]_clock_enable_0);
M1_q_b[1]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[1]_PORT_A_address_reg = DFFE(M1_q_b[1]_PORT_A_address, M1_q_b[1]_clock_0, , , M1_q_b[1]_clock_enable_0);
M1_q_b[1]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[1]_PORT_B_address_reg = DFFE(M1_q_b[1]_PORT_B_address, M1_q_b[1]_clock_1, , , );
M1_q_b[1]_PORT_A_write_enable = VCC;
M1_q_b[1]_PORT_A_write_enable_reg = DFFE(M1_q_b[1]_PORT_A_write_enable, M1_q_b[1]_clock_0, , , M1_q_b[1]_clock_enable_0);
M1_q_b[1]_PORT_B_read_enable = VCC;
M1_q_b[1]_PORT_B_read_enable_reg = DFFE(M1_q_b[1]_PORT_B_read_enable, M1_q_b[1]_clock_1, , , );
M1_q_b[1]_clock_0 = clk;
M1_q_b[1]_clock_1 = clk;
M1_q_b[1]_clock_enable_0 = wren1;
M1_q_b[1]_PORT_B_data_out = MEMORY(M1_q_b[1]_PORT_A_data_in_reg, , M1_q_b[1]_PORT_A_address_reg, M1_q_b[1]_PORT_B_address_reg, M1_q_b[1]_PORT_A_write_enable_reg, M1_q_b[1]_PORT_B_read_enable_reg, , , M1_q_b[1]_clock_0, M1_q_b[1]_clock_1, M1_q_b[1]_clock_enable_0, , , );
M1_q_b[1] = M1_q_b[1]_PORT_B_data_out[0];


--M1_q_b[0] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[0]_PORT_A_data_in = G2_drop_bits_node[0][0];
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , M1_q_b[0]_clock_enable_0);
M1_q_b[0]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , M1_q_b[0]_clock_enable_0);
M1_q_b[0]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_PORT_A_write_enable = VCC;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , M1_q_b[0]_clock_enable_0);
M1_q_b[0]_PORT_B_read_enable = VCC;
M1_q_b[0]_PORT_B_read_enable_reg = DFFE(M1_q_b[0]_PORT_B_read_enable, M1_q_b[0]_clock_1, , , );
M1_q_b[0]_clock_0 = clk;
M1_q_b[0]_clock_1 = clk;
M1_q_b[0]_clock_enable_0 = wren1;
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, , M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_read_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, M1_q_b[0]_clock_enable_0, , , );
M1_q_b[0] = M1_q_b[0]_PORT_B_data_out[0];


--K12L1 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~204
--operation mode is normal

K12L1_carry_eqn = K12L3;
K12L1 = K81_sout_node[9] $ (K12L1_carry_eqn);


--K12L2 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~209
--operation mode is arithmetic

K12L2_carry_eqn = K12L5;
K12L2 = K81_sout_node[8] $ (!K12L2_carry_eqn);

--K12L3 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~211
--operation mode is arithmetic

K12L3 = CARRY(K81_sout_node[8] & (!K12L5));


--K12L4 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~214
--operation mode is arithmetic

K12L4_carry_eqn = K12L7;
K12L4 = K81_sout_node[7] $ (K12L4_carry_eqn);

--K12L5 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~216
--operation mode is arithmetic

K12L5 = CARRY(!K12L7 # !K81_sout_node[7]);


--K12L6 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~219
--operation mode is arithmetic

K12L6_carry_eqn = K12L9;
K12L6 = K81_sout_node[6] $ (!K12L6_carry_eqn);

--K12L7 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~221
--operation mode is arithmetic

K12L7 = CARRY(K81_sout_node[6] & (!K12L9));


--K12L8 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~224
--operation mode is arithmetic

K12L8_carry_eqn = K12L11;
K12L8 = K51_sout_node[9] $ K81_sout_node[5] $ K12L8_carry_eqn;

--K12L9 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~226
--operation mode is arithmetic

K12L9 = CARRY(K51_sout_node[9] & !K81_sout_node[5] & !K12L11 # !K51_sout_node[9] & (!K12L11 # !K81_sout_node[5]));


--K12L01 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~229
--operation mode is arithmetic

K12L01_carry_eqn = K12L31;
K12L01 = K51_sout_node[8] $ K81_sout_node[4] $ !K12L01_carry_eqn;

--K12L11 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~231
--operation mode is arithmetic

K12L11 = CARRY(K51_sout_node[8] & (K81_sout_node[4] # !K12L31) # !K51_sout_node[8] & K81_sout_node[4] & !K12L31);


--K12L21 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~234
--operation mode is arithmetic

K12L21_carry_eqn = K12L51;
K12L21 = K51_sout_node[7] $ K81_sout_node[3] $ K12L21_carry_eqn;

--K12L31 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~236
--operation mode is arithmetic

K12L31 = CARRY(K51_sout_node[7] & !K81_sout_node[3] & !K12L51 # !K51_sout_node[7] & (!K12L51 # !K81_sout_node[3]));