pipemult.map.eqn

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

-- Copyright (C) 1991-2005 Altera Corporation
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-- without limitation, that your use is for the sole purpose of 
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--M1_q_b[15] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[15]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[15]_PORT_A_data_in = K12L1;
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = clk;
M1_q_b[15]_clock_1 = clk;
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[15] = M1_q_b[15]_PORT_B_data_out[0];


--M1_q_b[14] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[14]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[14]_PORT_A_data_in = K12L2;
M1_q_b[14]_PORT_A_data_in_reg = DFFE(M1_q_b[14]_PORT_A_data_in, M1_q_b[14]_clock_0, , , M1_q_b[14]_clock_enable_0);
M1_q_b[14]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[14]_PORT_A_address_reg = DFFE(M1_q_b[14]_PORT_A_address, M1_q_b[14]_clock_0, , , M1_q_b[14]_clock_enable_0);
M1_q_b[14]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[14]_PORT_B_address_reg = DFFE(M1_q_b[14]_PORT_B_address, M1_q_b[14]_clock_1, , , );
M1_q_b[14]_PORT_A_write_enable = VCC;
M1_q_b[14]_PORT_A_write_enable_reg = DFFE(M1_q_b[14]_PORT_A_write_enable, M1_q_b[14]_clock_0, , , M1_q_b[14]_clock_enable_0);
M1_q_b[14]_PORT_B_read_enable = VCC;
M1_q_b[14]_PORT_B_read_enable_reg = DFFE(M1_q_b[14]_PORT_B_read_enable, M1_q_b[14]_clock_1, , , );
M1_q_b[14]_clock_0 = clk;
M1_q_b[14]_clock_1 = clk;
M1_q_b[14]_clock_enable_0 = wren1;
M1_q_b[14]_PORT_B_data_out = MEMORY(M1_q_b[14]_PORT_A_data_in_reg, , M1_q_b[14]_PORT_A_address_reg, M1_q_b[14]_PORT_B_address_reg, M1_q_b[14]_PORT_A_write_enable_reg, M1_q_b[14]_PORT_B_read_enable_reg, , , M1_q_b[14]_clock_0, M1_q_b[14]_clock_1, M1_q_b[14]_clock_enable_0, , , );
M1_q_b[14] = M1_q_b[14]_PORT_B_data_out[0];


--M1_q_b[13] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[13]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[13]_PORT_A_data_in = K12L4;
M1_q_b[13]_PORT_A_data_in_reg = DFFE(M1_q_b[13]_PORT_A_data_in, M1_q_b[13]_clock_0, , , M1_q_b[13]_clock_enable_0);
M1_q_b[13]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[13]_PORT_A_address_reg = DFFE(M1_q_b[13]_PORT_A_address, M1_q_b[13]_clock_0, , , M1_q_b[13]_clock_enable_0);
M1_q_b[13]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[13]_PORT_B_address_reg = DFFE(M1_q_b[13]_PORT_B_address, M1_q_b[13]_clock_1, , , );
M1_q_b[13]_PORT_A_write_enable = VCC;
M1_q_b[13]_PORT_A_write_enable_reg = DFFE(M1_q_b[13]_PORT_A_write_enable, M1_q_b[13]_clock_0, , , M1_q_b[13]_clock_enable_0);
M1_q_b[13]_PORT_B_read_enable = VCC;
M1_q_b[13]_PORT_B_read_enable_reg = DFFE(M1_q_b[13]_PORT_B_read_enable, M1_q_b[13]_clock_1, , , );
M1_q_b[13]_clock_0 = clk;
M1_q_b[13]_clock_1 = clk;
M1_q_b[13]_clock_enable_0 = wren1;
M1_q_b[13]_PORT_B_data_out = MEMORY(M1_q_b[13]_PORT_A_data_in_reg, , M1_q_b[13]_PORT_A_address_reg, M1_q_b[13]_PORT_B_address_reg, M1_q_b[13]_PORT_A_write_enable_reg, M1_q_b[13]_PORT_B_read_enable_reg, , , M1_q_b[13]_clock_0, M1_q_b[13]_clock_1, M1_q_b[13]_clock_enable_0, , , );
M1_q_b[13] = M1_q_b[13]_PORT_B_data_out[0];


--M1_q_b[12] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[12]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[12]_PORT_A_data_in = K12L6;
M1_q_b[12]_PORT_A_data_in_reg = DFFE(M1_q_b[12]_PORT_A_data_in, M1_q_b[12]_clock_0, , , M1_q_b[12]_clock_enable_0);
M1_q_b[12]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[12]_PORT_A_address_reg = DFFE(M1_q_b[12]_PORT_A_address, M1_q_b[12]_clock_0, , , M1_q_b[12]_clock_enable_0);
M1_q_b[12]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[12]_PORT_B_address_reg = DFFE(M1_q_b[12]_PORT_B_address, M1_q_b[12]_clock_1, , , );
M1_q_b[12]_PORT_A_write_enable = VCC;
M1_q_b[12]_PORT_A_write_enable_reg = DFFE(M1_q_b[12]_PORT_A_write_enable, M1_q_b[12]_clock_0, , , M1_q_b[12]_clock_enable_0);
M1_q_b[12]_PORT_B_read_enable = VCC;
M1_q_b[12]_PORT_B_read_enable_reg = DFFE(M1_q_b[12]_PORT_B_read_enable, M1_q_b[12]_clock_1, , , );
M1_q_b[12]_clock_0 = clk;
M1_q_b[12]_clock_1 = clk;
M1_q_b[12]_clock_enable_0 = wren1;
M1_q_b[12]_PORT_B_data_out = MEMORY(M1_q_b[12]_PORT_A_data_in_reg, , M1_q_b[12]_PORT_A_address_reg, M1_q_b[12]_PORT_B_address_reg, M1_q_b[12]_PORT_A_write_enable_reg, M1_q_b[12]_PORT_B_read_enable_reg, , , M1_q_b[12]_clock_0, M1_q_b[12]_clock_1, M1_q_b[12]_clock_enable_0, , , );
M1_q_b[12] = M1_q_b[12]_PORT_B_data_out[0];


--M1_q_b[11] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[11]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[11]_PORT_A_data_in = K12L8;
M1_q_b[11]_PORT_A_data_in_reg = DFFE(M1_q_b[11]_PORT_A_data_in, M1_q_b[11]_clock_0, , , M1_q_b[11]_clock_enable_0);
M1_q_b[11]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[11]_PORT_A_address_reg = DFFE(M1_q_b[11]_PORT_A_address, M1_q_b[11]_clock_0, , , M1_q_b[11]_clock_enable_0);
M1_q_b[11]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[11]_PORT_B_address_reg = DFFE(M1_q_b[11]_PORT_B_address, M1_q_b[11]_clock_1, , , );
M1_q_b[11]_PORT_A_write_enable = VCC;
M1_q_b[11]_PORT_A_write_enable_reg = DFFE(M1_q_b[11]_PORT_A_write_enable, M1_q_b[11]_clock_0, , , M1_q_b[11]_clock_enable_0);
M1_q_b[11]_PORT_B_read_enable = VCC;
M1_q_b[11]_PORT_B_read_enable_reg = DFFE(M1_q_b[11]_PORT_B_read_enable, M1_q_b[11]_clock_1, , , );
M1_q_b[11]_clock_0 = clk;
M1_q_b[11]_clock_1 = clk;
M1_q_b[11]_clock_enable_0 = wren1;
M1_q_b[11]_PORT_B_data_out = MEMORY(M1_q_b[11]_PORT_A_data_in_reg, , M1_q_b[11]_PORT_A_address_reg, M1_q_b[11]_PORT_B_address_reg, M1_q_b[11]_PORT_A_write_enable_reg, M1_q_b[11]_PORT_B_read_enable_reg, , , M1_q_b[11]_clock_0, M1_q_b[11]_clock_1, M1_q_b[11]_clock_enable_0, , , );
M1_q_b[11] = M1_q_b[11]_PORT_B_data_out[0];


--M1_q_b[10] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[10]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[10]_PORT_A_data_in = K12L01;
M1_q_b[10]_PORT_A_data_in_reg = DFFE(M1_q_b[10]_PORT_A_data_in, M1_q_b[10]_clock_0, , , M1_q_b[10]_clock_enable_0);
M1_q_b[10]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[10]_PORT_A_address_reg = DFFE(M1_q_b[10]_PORT_A_address, M1_q_b[10]_clock_0, , , M1_q_b[10]_clock_enable_0);
M1_q_b[10]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[10]_PORT_B_address_reg = DFFE(M1_q_b[10]_PORT_B_address, M1_q_b[10]_clock_1, , , );
M1_q_b[10]_PORT_A_write_enable = VCC;
M1_q_b[10]_PORT_A_write_enable_reg = DFFE(M1_q_b[10]_PORT_A_write_enable, M1_q_b[10]_clock_0, , , M1_q_b[10]_clock_enable_0);
M1_q_b[10]_PORT_B_read_enable = VCC;
M1_q_b[10]_PORT_B_read_enable_reg = DFFE(M1_q_b[10]_PORT_B_read_enable, M1_q_b[10]_clock_1, , , );
M1_q_b[10]_clock_0 = clk;
M1_q_b[10]_clock_1 = clk;
M1_q_b[10]_clock_enable_0 = wren1;
M1_q_b[10]_PORT_B_data_out = MEMORY(M1_q_b[10]_PORT_A_data_in_reg, , M1_q_b[10]_PORT_A_address_reg, M1_q_b[10]_PORT_B_address_reg, M1_q_b[10]_PORT_A_write_enable_reg, M1_q_b[10]_PORT_B_read_enable_reg, , , M1_q_b[10]_clock_0, M1_q_b[10]_clock_1, M1_q_b[10]_clock_enable_0, , , );
M1_q_b[10] = M1_q_b[10]_PORT_B_data_out[0];


--M1_q_b[9] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[9]_PORT_A_data_in = K12L21;
M1_q_b[9]_PORT_A_data_in_reg = DFFE(M1_q_b[9]_PORT_A_data_in, M1_q_b[9]_clock_0, , , M1_q_b[9]_clock_enable_0);
M1_q_b[9]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[9]_PORT_A_address_reg = DFFE(M1_q_b[9]_PORT_A_address, M1_q_b[9]_clock_0, , , M1_q_b[9]_clock_enable_0);
M1_q_b[9]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[9]_PORT_B_address_reg = DFFE(M1_q_b[9]_PORT_B_address, M1_q_b[9]_clock_1, , , );
M1_q_b[9]_PORT_A_write_enable = VCC;
M1_q_b[9]_PORT_A_write_enable_reg = DFFE(M1_q_b[9]_PORT_A_write_enable, M1_q_b[9]_clock_0, , , M1_q_b[9]_clock_enable_0);
M1_q_b[9]_PORT_B_read_enable = VCC;
M1_q_b[9]_PORT_B_read_enable_reg = DFFE(M1_q_b[9]_PORT_B_read_enable, M1_q_b[9]_clock_1, , , );
M1_q_b[9]_clock_0 = clk;
M1_q_b[9]_clock_1 = clk;
M1_q_b[9]_clock_enable_0 = wren1;
M1_q_b[9]_PORT_B_data_out = MEMORY(M1_q_b[9]_PORT_A_data_in_reg, , M1_q_b[9]_PORT_A_address_reg, M1_q_b[9]_PORT_B_address_reg, M1_q_b[9]_PORT_A_write_enable_reg, M1_q_b[9]_PORT_B_read_enable_reg, , , M1_q_b[9]_clock_0, M1_q_b[9]_clock_1, M1_q_b[9]_clock_enable_0, , , );
M1_q_b[9] = M1_q_b[9]_PORT_B_data_out[0];


--M1_q_b[8] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[8]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[8]_PORT_A_data_in = K12L41;
M1_q_b[8]_PORT_A_data_in_reg = DFFE(M1_q_b[8]_PORT_A_data_in, M1_q_b[8]_clock_0, , , M1_q_b[8]_clock_enable_0);
M1_q_b[8]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[8]_PORT_A_address_reg = DFFE(M1_q_b[8]_PORT_A_address, M1_q_b[8]_clock_0, , , M1_q_b[8]_clock_enable_0);
M1_q_b[8]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[8]_PORT_B_address_reg = DFFE(M1_q_b[8]_PORT_B_address, M1_q_b[8]_clock_1, , , );
M1_q_b[8]_PORT_A_write_enable = VCC;
M1_q_b[8]_PORT_A_write_enable_reg = DFFE(M1_q_b[8]_PORT_A_write_enable, M1_q_b[8]_clock_0, , , M1_q_b[8]_clock_enable_0);
M1_q_b[8]_PORT_B_read_enable = VCC;
M1_q_b[8]_PORT_B_read_enable_reg = DFFE(M1_q_b[8]_PORT_B_read_enable, M1_q_b[8]_clock_1, , , );
M1_q_b[8]_clock_0 = clk;
M1_q_b[8]_clock_1 = clk;
M1_q_b[8]_clock_enable_0 = wren1;
M1_q_b[8]_PORT_B_data_out = MEMORY(M1_q_b[8]_PORT_A_data_in_reg, , M1_q_b[8]_PORT_A_address_reg, M1_q_b[8]_PORT_B_address_reg, M1_q_b[8]_PORT_A_write_enable_reg, M1_q_b[8]_PORT_B_read_enable_reg, , , M1_q_b[8]_clock_0, M1_q_b[8]_clock_1, M1_q_b[8]_clock_enable_0, , , );
M1_q_b[8] = M1_q_b[8]_PORT_B_data_out[0];


--M1_q_b[7] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[7]_PORT_A_data_in = K12L61;
M1_q_b[7]_PORT_A_data_in_reg = DFFE(M1_q_b[7]_PORT_A_data_in, M1_q_b[7]_clock_0, , , M1_q_b[7]_clock_enable_0);
M1_q_b[7]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[7]_PORT_A_address_reg = DFFE(M1_q_b[7]_PORT_A_address, M1_q_b[7]_clock_0, , , M1_q_b[7]_clock_enable_0);
M1_q_b[7]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[7]_PORT_B_address_reg = DFFE(M1_q_b[7]_PORT_B_address, M1_q_b[7]_clock_1, , , );
M1_q_b[7]_PORT_A_write_enable = VCC;
M1_q_b[7]_PORT_A_write_enable_reg = DFFE(M1_q_b[7]_PORT_A_write_enable, M1_q_b[7]_clock_0, , , M1_q_b[7]_clock_enable_0);
M1_q_b[7]_PORT_B_read_enable = VCC;
M1_q_b[7]_PORT_B_read_enable_reg = DFFE(M1_q_b[7]_PORT_B_read_enable, M1_q_b[7]_clock_1, , , );
M1_q_b[7]_clock_0 = clk;
M1_q_b[7]_clock_1 = clk;
M1_q_b[7]_clock_enable_0 = wren1;
M1_q_b[7]_PORT_B_data_out = MEMORY(M1_q_b[7]_PORT_A_data_in_reg, , M1_q_b[7]_PORT_A_address_reg, M1_q_b[7]_PORT_B_address_reg, M1_q_b[7]_PORT_A_write_enable_reg, M1_q_b[7]_PORT_B_read_enable_reg, , , M1_q_b[7]_clock_0, M1_q_b[7]_clock_1, M1_q_b[7]_clock_enable_0, , , );
M1_q_b[7] = M1_q_b[7]_PORT_B_data_out[0];


--M1_q_b[6] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[6]_PORT_A_data_in = K12L81;
M1_q_b[6]_PORT_A_data_in_reg = DFFE(M1_q_b[6]_PORT_A_data_in, M1_q_b[6]_clock_0, , , M1_q_b[6]_clock_enable_0);
M1_q_b[6]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[6]_PORT_A_address_reg = DFFE(M1_q_b[6]_PORT_A_address, M1_q_b[6]_clock_0, , , M1_q_b[6]_clock_enable_0);
M1_q_b[6]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);