pipemult.vqm

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~226 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~226COUT1_270 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~221 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~221COUT1_271 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~216 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~216COUT1_272 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~211 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~204 ;
wire \wraddress1[0]~combout ;
wire \wraddress1[1]~combout ;
wire \wraddress1[2]~combout ;
wire \wraddress1[3]~combout ;
wire \wraddress1[4]~combout ;
wire \rdaddress1[0]~combout ;
wire \rdaddress1[1]~combout ;
wire \rdaddress1[2]~combout ;
wire \rdaddress1[3]~combout ;
wire \rdaddress1[4]~combout ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~209 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~214 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~219 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~224 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~229 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~234 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~239 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~244 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~249 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~254 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~259 ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|sout_node[1] ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|sout_node[0] ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|drop_bits_node[0][1] ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|decoder_node[0][0] ;
wire \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|drop_bits_node[0][0] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[15] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[14] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[13] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[12] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[11] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[10] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[9] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[8] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[7] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[6] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[5] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[4] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[3] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[2] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[1] ;
wire \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[0] ;
wire [9:0] \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node ;
wire [9:0] \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|sout_node ;
wire [15:0] \ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b ;


wire gnd;
wire vcc;

assign gnd = 1'b0;
assign vcc = 1'b1;


cyclone_io \clk~I (
	.combout(\clk~combout ),
	.padio(clk));
defparam \clk~I .operation_mode = "input";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .output_sync_reset = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .oe_power_up = "low";

cyclone_io \wren1~I (
	.combout(\wren1~combout ),
	.padio(wren1));
defparam \wren1~I .operation_mode = "input";
defparam \wren1~I .input_register_mode = "none";
defparam \wren1~I .output_register_mode = "none";
defparam \wren1~I .oe_register_mode = "none";
defparam \wren1~I .input_async_reset = "none";
defparam \wren1~I .output_async_reset = "none";
defparam \wren1~I .oe_async_reset = "none";
defparam \wren1~I .input_sync_reset = "none";
defparam \wren1~I .output_sync_reset = "none";
defparam \wren1~I .oe_sync_reset = "none";
defparam \wren1~I .input_power_up = "low";
defparam \wren1~I .output_power_up = "low";
defparam \wren1~I .oe_power_up = "low";

cyclone_io \datab[7]~I (
	.combout(\datab[7]~combout ),
	.padio(datab[7]));
defparam \datab[7]~I .operation_mode = "input";
defparam \datab[7]~I .input_register_mode = "none";
defparam \datab[7]~I .output_register_mode = "none";
defparam \datab[7]~I .oe_register_mode = "none";
defparam \datab[7]~I .input_async_reset = "none";
defparam \datab[7]~I .output_async_reset = "none";
defparam \datab[7]~I .oe_async_reset = "none";
defparam \datab[7]~I .input_sync_reset = "none";
defparam \datab[7]~I .output_sync_reset = "none";
defparam \datab[7]~I .oe_sync_reset = "none";
defparam \datab[7]~I .input_power_up = "low";
defparam \datab[7]~I .output_power_up = "low";
defparam \datab[7]~I .oe_power_up = "low";

cyclone_io \dataa[4]~I (
	.combout(\dataa[4]~combout ),
	.padio(dataa[4]));
defparam \dataa[4]~I .operation_mode = "input";
defparam \dataa[4]~I .input_register_mode = "none";
defparam \dataa[4]~I .output_register_mode = "none";
defparam \dataa[4]~I .oe_register_mode = "none";
defparam \dataa[4]~I .input_async_reset = "none";
defparam \dataa[4]~I .output_async_reset = "none";
defparam \dataa[4]~I .oe_async_reset = "none";
defparam \dataa[4]~I .input_sync_reset = "none";
defparam \dataa[4]~I .output_sync_reset = "none";
defparam \dataa[4]~I .oe_sync_reset = "none";
defparam \dataa[4]~I .input_power_up = "low";
defparam \dataa[4]~I .output_power_up = "low";
defparam \dataa[4]~I .oe_power_up = "low";

cyclone_lcell \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|decoder_node[7][4]~I (
	.clk(\clk~combout ),
	.datac(\datab[7]~combout ),
	.datad(\dataa[4]~combout ),
	.aclr(gnd),
	.regout(\mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|decoder_node[7][4] ));
defparam \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|decoder_node[7][4]~I .operation_mode = "normal";
defparam \mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|decoder_node[7][4]~I .synch_mode = "off";