pipemult.fit.eqn

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[9] = M1_q_b[15]_PORT_B_data_out[6];

--M1_q_b[10] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[10] at M4K_X17_Y1
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[10] = M1_q_b[15]_PORT_B_data_out[5];

--M1_q_b[11] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[11] at M4K_X17_Y1
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[11] = M1_q_b[15]_PORT_B_data_out[4];

--M1_q_b[12] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[12] at M4K_X17_Y1
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[12] = M1_q_b[15]_PORT_B_data_out[3];

--M1_q_b[13] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[13] at M4K_X17_Y1
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[13] = M1_q_b[15]_PORT_B_data_out[2];

--M1_q_b[14] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[14] at M4K_X17_Y1
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[14] = M1_q_b[15]_PORT_B_data_out[1];


--K12L1 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~204 at LC_X19_Y1_N5
--operation mode is normal

K12L1_carry_eqn = K12L3;
K12L1 = K12L1_carry_eqn $ K81_sout_node[9];


--K12L2 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~209 at LC_X19_Y1_N4
--operation mode is arithmetic

K12L2_carry_eqn = (!K12L71 & K12L5) # (K12L71 & K12L6);
K12L2 = K81_sout_node[8] $ !K12L2_carry_eqn;

--K12L3 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~211 at LC_X19_Y1_N4
--operation mode is arithmetic

K12L3 = CARRY(K81_sout_node[8] & !K12L6);


--K12L4 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~214 at LC_X19_Y1_N3
--operation mode is arithmetic

K12L4_carry_eqn = (!K12L71 & K12L8) # (K12L71 & K12L9);
K12L4 = K81_sout_node[7] $ K12L4_carry_eqn;

--K12L5 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~216 at LC_X19_Y1_N3
--operation mode is arithmetic

K12L5_cout_0 = !K12L8 # !K81_sout_node[7];
K12L5 = CARRY(K12L5_cout_0);

--K12L6 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~216COUT1_272 at LC_X19_Y1_N3
--operation mode is arithmetic

K12L6_cout_1 = !K12L9 # !K81_sout_node[7];
K12L6 = CARRY(K12L6_cout_1);


--K12L7 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~219 at LC_X19_Y1_N2
--operation mode is arithmetic

K12L7_carry_eqn = (!K12L71 & K12L11) # (K12L71 & K12L21);
K12L7 = K81_sout_node[6] $ !K12L7_carry_eqn;

--K12L8 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~221 at LC_X19_Y1_N2
--operation mode is arithmetic

K12L8_cout_0 = K81_sout_node[6] & !K12L11;
K12L8 = CARRY(K12L8_cout_0);

--K12L9 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~221COUT1_271 at LC_X19_Y1_N2
--operation mode is arithmetic

K12L9_cout_1 = K81_sout_node[6] & !K12L21;
K12L9 = CARRY(K12L9_cout_1);


--K12L01 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~224 at LC_X19_Y1_N1
--operation mode is arithmetic

K12L01_carry_eqn = (!K12L71 & K12L41) # (K12L71 & K12L51);
K12L01 = K51_sout_node[9] $ K81_sout_node[5] $ K12L01_carry_eqn;

--K12L11 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~226 at LC_X19_Y1_N1
--operation mode is arithmetic

K12L11_cout_0 = K51_sout_node[9] & !K81_sout_node[5] & !K12L41 # !K51_sout_node[9] & (!K12L41 # !K81_sout_node[5]);
K12L11 = CARRY(K12L11_cout_0);

--K12L21 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~226COUT1_270 at LC_X19_Y1_N1
--operation mode is arithmetic

K12L21_cout_1 = K51_sout_node[9] & !K81_sout_node[5] & !K12L51 # !K51_sout_node[9] & (!K12L51 # !K81_sout_node[5]);
K12L21 = CARRY(K12L21_cout_1);


--K12L31 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~229 at LC_X19_Y1_N0
--operation mode is arithmetic

K12L31_carry_eqn = K12L71;
K12L31 = K81_sout_node[4] $ K51_sout_node[8] $ !K12L31_carry_eqn;

--K12L41 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~231 at LC_X19_Y1_N0
--operation mode is arithmetic

K12L41_cout_0 = K81_sout_node[4] & (K51_sout_node[8] # !K12L71) # !K81_sout_node[4] & K51_sout_node[8] & !K12L71;
K12L41 = CARRY(K12L41_cout_0);

--K12L51 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~231COUT1_269 at LC_X19_Y1_N0
--operation mode is arithmetic

K12L51_cout_1 = K81_sout_node[4] & (K51_sout_node[8] # !K12L71) # !K81_sout_node[4] & K51_sout_node[8] & !K12L71;
K12L51 = CARRY(K12L51_cout_1);


--K12L61 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~234 at LC_X19_Y2_N9
--operation mode is arithmetic

K12L61_carry_eqn = (!K12L13 & K12L91) # (K12L13 & K12L02);
K12L61 = K81_sout_node[3] $ K51_sout_node[7] $ K12L61_carry_eqn;

--K12L71 is mult:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~236 at LC_X19_Y2_N9
--operation mode is arithmetic