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📁 郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--M1_q_b[15] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[15] at M4K_X17_Y1
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 16, Port B Depth: 32, Port B Width: 16
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[15] = M1_q_b[15]_PORT_B_data_out[0];

--M1_q_b[0] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[0] at M4K_X17_Y1
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[0] = M1_q_b[15]_PORT_B_data_out[15];

--M1_q_b[1] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[1] at M4K_X17_Y1
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[1] = M1_q_b[15]_PORT_B_data_out[14];

--M1_q_b[2] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[2] at M4K_X17_Y1
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[2] = M1_q_b[15]_PORT_B_data_out[13];

--M1_q_b[3] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[3] at M4K_X17_Y1
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[3] = M1_q_b[15]_PORT_B_data_out[12];

--M1_q_b[4] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[4] at M4K_X17_Y1
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[4] = M1_q_b[15]_PORT_B_data_out[11];

--M1_q_b[5] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[5] at M4K_X17_Y1
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[5] = M1_q_b[15]_PORT_B_data_out[10];

--M1_q_b[6] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[6] at M4K_X17_Y1
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[6] = M1_q_b[15]_PORT_B_data_out[9];

--M1_q_b[7] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[7] at M4K_X17_Y1
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[7] = M1_q_b[15]_PORT_B_data_out[8];

--M1_q_b[8] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[8] at M4K_X17_Y1
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
M1_q_b[15]_PORT_B_read_enable_reg = DFFE(M1_q_b[15]_PORT_B_read_enable, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_clock_0 = GLOBAL(clk);
M1_q_b[15]_clock_1 = GLOBAL(clk);
M1_q_b[15]_clock_enable_0 = wren1;
M1_q_b[15]_PORT_B_data_out = MEMORY(M1_q_b[15]_PORT_A_data_in_reg, , M1_q_b[15]_PORT_A_address_reg, M1_q_b[15]_PORT_B_address_reg, M1_q_b[15]_PORT_A_write_enable_reg, M1_q_b[15]_PORT_B_read_enable_reg, , , M1_q_b[15]_clock_0, M1_q_b[15]_clock_1, M1_q_b[15]_clock_enable_0, , , );
M1_q_b[8] = M1_q_b[15]_PORT_B_data_out[7];

--M1_q_b[9] is ram:inst1|altsyncram:altsyncram_component|altsyncram_j6b1:auto_generated|q_b[9] at M4K_X17_Y1
M1_q_b[15]_PORT_A_data_in = BUS(K12L1, K12L2, K12L4, K12L7, K12L01, K12L31, K12L61, K12L81, K12L12, K12L42, K12L72, K12L03, K51_sout_node[1], K51_sout_node[0], G2_drop_bits_node[0][1], G2_drop_bits_node[0][0]);
M1_q_b[15]_PORT_A_data_in_reg = DFFE(M1_q_b[15]_PORT_A_data_in, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_A_address = BUS(wraddress1[0], wraddress1[1], wraddress1[2], wraddress1[3], wraddress1[4]);
M1_q_b[15]_PORT_A_address_reg = DFFE(M1_q_b[15]_PORT_A_address, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_address = BUS(rdaddress1[0], rdaddress1[1], rdaddress1[2], rdaddress1[3], rdaddress1[4]);
M1_q_b[15]_PORT_B_address_reg = DFFE(M1_q_b[15]_PORT_B_address, M1_q_b[15]_clock_1, , , );
M1_q_b[15]_PORT_A_write_enable = VCC;
M1_q_b[15]_PORT_A_write_enable_reg = DFFE(M1_q_b[15]_PORT_A_write_enable, M1_q_b[15]_clock_0, , , M1_q_b[15]_clock_enable_0);
M1_q_b[15]_PORT_B_read_enable = VCC;
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