addere.tan.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 05 11:29:46 2006 " "Info: Processing started: Fri May 05 11:29:46 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off AdderE -c AdderE --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off AdderE -c AdderE --timing_analysis_only" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "A\[0\] COUT 16.351 ns Longest " "Info: Longest tpd from source pin \"A\[0\]\" to destination pin \"COUT\" is 16.351 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns A\[0\] 1 PIN PIN_B7 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_B7; Fanout = 2; PIN Node = 'A\[0\]'" {  } { { "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" "" { Report "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" Compiler "AdderE" "UNKNOWN" "V1" "E:/QProj/AdderEQ/db/AdderE.quartus_db" { Floorplan "E:/QProj/AdderEQ/" "" "" { A[0] } "NODE_NAME" } "" } } { "synplify_work/AdderE.vqm" "" { Text "E:/QProj/AdderEQ/synplify_work/AdderE.vqm" 396 16 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.331 ns) + CELL(0.442 ns) 7.248 ns Full_Adder:Stages_0_LowBit_FA\|COUT_x 2 COMB LC_X14_Y20_N2 2 " "Info: 2: + IC(5.331 ns) + CELL(0.442 ns) = 7.248 ns; Loc. = LC_X14_Y20_N2; Fanout = 2; COMB Node = 'Full_Adder:Stages_0_LowBit_FA\|COUT_x'" {  } { { "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" "" { Report "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" Compiler "AdderE" "UNKNOWN" "V1" "E:/QProj/AdderEQ/db/AdderE.quartus_db" { Floorplan "E:/QProj/AdderEQ/" "" "5.773 ns" { A[0] Full_Adder:Stages_0_LowBit_FA|COUT_x } "NODE_NAME" } "" } } { "synplify_work/AdderE.vqm" "" { Text "E:/QProj/AdderEQ/synplify_work/AdderE.vqm" 22 16 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.453 ns) + CELL(0.292 ns) 7.993 ns Full_Adder_2:Stages_1_OtherBits_FA\|COUT_x_0 3 COMB LC_X14_Y20_N5 2 " "Info: 3: + IC(0.453 ns) + CELL(0.292 ns) = 7.993 ns; Loc. = LC_X14_Y20_N5; Fanout = 2; COMB Node = 'Full_Adder_2:Stages_1_OtherBits_FA\|COUT_x_0'" {  } { { "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" "" { Report "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" Compiler "AdderE" "UNKNOWN" "V1" "E:/QProj/AdderEQ/db/AdderE.quartus_db" { Floorplan "E:/QProj/AdderEQ/" "" "0.745 ns" { Full_Adder:Stages_0_LowBit_FA|COUT_x Full_Adder_2:Stages_1_OtherBits_FA|COUT_x_0 } "NODE_NAME" } "" } } { "synplify_work/AdderE.vqm" "" { Text "E:/QProj/AdderEQ/synplify_work/AdderE.vqm" 116 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.431 ns) + CELL(0.114 ns) 8.538 ns Full_Adder_5:Stages_2_OtherBits_FA\|COUT_x_0 4 COMB LC_X14_Y20_N9 2 " "Info: 4: + IC(0.431 ns) + CELL(0.114 ns) = 8.538 ns; Loc. = LC_X14_Y20_N9; Fanout = 2; COMB Node = 'Full_Adder_5:Stages_2_OtherBits_FA\|COUT_x_0'" {  } { { "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" "" { Report "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" Compiler "AdderE" "UNKNOWN" "V1" "E:/QProj/AdderEQ/db/AdderE.quartus_db" { Floorplan "E:/QProj/AdderEQ/" "" "0.545 ns" { Full_Adder_2:Stages_1_OtherBits_FA|COUT_x_0 Full_Adder_5:Stages_2_OtherBits_FA|COUT_x_0 } "NODE_NAME" } "" } } { "synplify_work/AdderE.vqm" "" { Text "E:/QProj/AdderEQ/synplify_work/AdderE.vqm" 257 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.788 ns) + CELL(0.114 ns) 10.440 ns Full_Adder_6:Stages_3_OtherBits_FA\|COUT_x_0 5 COMB LC_X3_Y20_N7 2 " "Info: 5: + IC(1.788 ns) + CELL(0.114 ns) = 10.440 ns; Loc. = LC_X3_Y20_N7; Fanout = 2; COMB Node = 'Full_Adder_6:Stages_3_OtherBits_FA\|COUT_x_0'" {  } { { "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" "" { Report "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" Compiler "AdderE" "UNKNOWN" "V1" "E:/QProj/AdderEQ/db/AdderE.quartus_db" { Floorplan "E:/QProj/AdderEQ/" "" "1.902 ns" { Full_Adder_5:Stages_2_OtherBits_FA|COUT_x_0 Full_Adder_6:Stages_3_OtherBits_FA|COUT_x_0 } "NODE_NAME" } "" } } { "synplify_work/AdderE.vqm" "" { Text "E:/QProj/AdderEQ/synplify_work/AdderE.vqm" 304 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.292 ns) 11.183 ns Full_Adder_7:Stages_4_OtherBits_FA\|COUT_x_0 6 COMB LC_X3_Y20_N3 2 " "Info: 6: + IC(0.451 ns) + CELL(0.292 ns) = 11.183 ns; Loc. = LC_X3_Y20_N3; Fanout = 2; COMB Node = 'Full_Adder_7:Stages_4_OtherBits_FA\|COUT_x_0'" {  } { { "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" "" { Report "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" Compiler "AdderE" "UNKNOWN" "V1" "E:/QProj/AdderEQ/db/AdderE.quartus_db" { Floorplan "E:/QProj/AdderEQ/" "" "0.743 ns" { Full_Adder_6:Stages_3_OtherBits_FA|COUT_x_0 Full_Adder_7:Stages_4_OtherBits_FA|COUT_x_0 } "NODE_NAME" } "" } } { "synplify_work/AdderE.vqm" "" { Text "E:/QProj/AdderEQ/synplify_work/AdderE.vqm" 351 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.114 ns) 11.739 ns Full_Adder_4:Stages_5_OtherBits_FA\|COUT_x_0 7 COMB LC_X3_Y20_N5 2 " "Info: 7: + IC(0.442 ns) + CELL(0.114 ns) = 11.739 ns; Loc. = LC_X3_Y20_N5; Fanout = 2; COMB Node = 'Full_Adder_4:Stages_5_OtherBits_FA\|COUT_x_0'" {  } { { "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" "" { Report "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" Compiler "AdderE" "UNKNOWN" "V1" "E:/QProj/AdderEQ/db/AdderE.quartus_db" { Floorplan "E:/QProj/AdderEQ/" "" "0.556 ns" { Full_Adder_7:Stages_4_OtherBits_FA|COUT_x_0 Full_Adder_4:Stages_5_OtherBits_FA|COUT_x_0 } "NODE_NAME" } "" } } { "synplify_work/AdderE.vqm" "" { Text "E:/QProj/AdderEQ/synplify_work/AdderE.vqm" 210 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.444 ns) + CELL(0.114 ns) 12.297 ns Full_Adder_1:Stages_6_OtherBits_FA\|COUT_x_0 8 COMB LC_X3_Y20_N1 2 " "Info: 8: + IC(0.444 ns) + CELL(0.114 ns) = 12.297 ns; Loc. = LC_X3_Y20_N1; Fanout = 2; COMB Node = 'Full_Adder_1:Stages_6_OtherBits_FA\|COUT_x_0'" {  } { { "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" "" { Report "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" Compiler "AdderE" "UNKNOWN" "V1" "E:/QProj/AdderEQ/db/AdderE.quartus_db" { Floorplan "E:/QProj/AdderEQ/" "" "0.558 ns" { Full_Adder_4:Stages_5_OtherBits_FA|COUT_x_0 Full_Adder_1:Stages_6_OtherBits_FA|COUT_x_0 } "NODE_NAME" } "" } } { "synplify_work/AdderE.vqm" "" { Text "E:/QProj/AdderEQ/synplify_work/AdderE.vqm" 69 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.114 ns) 12.853 ns Full_Adder_3:Stages_7_OtherBits_FA\|N_5_i 9 COMB LC_X3_Y20_N2 1 " "Info: 9: + IC(0.442 ns) + CELL(0.114 ns) = 12.853 ns; Loc. = LC_X3_Y20_N2; Fanout = 1; COMB Node = 'Full_Adder_3:Stages_7_OtherBits_FA\|N_5_i'" {  } { { "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" "" { Report "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" Compiler "AdderE" "UNKNOWN" "V1" "E:/QProj/AdderEQ/db/AdderE.quartus_db" { Floorplan "E:/QProj/AdderEQ/" "" "0.556 ns" { Full_Adder_1:Stages_6_OtherBits_FA|COUT_x_0 Full_Adder_3:Stages_7_OtherBits_FA|N_5_i } "NODE_NAME" } "" } } { "synplify_work/AdderE.vqm" "" { Text "E:/QProj/AdderEQ/synplify_work/AdderE.vqm" 163 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.374 ns) + CELL(2.124 ns) 16.351 ns COUT 10 PIN PIN_C3 0 " "Info: 10: + IC(1.374 ns) + CELL(2.124 ns) = 16.351 ns; Loc. = PIN_C3; Fanout = 0; PIN Node = 'COUT'" {  } { { "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" "" { Report "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" Compiler "AdderE" "UNKNOWN" "V1" "E:/QProj/AdderEQ/db/AdderE.quartus_db" { Floorplan "E:/QProj/AdderEQ/" "" "3.498 ns" { Full_Adder_3:Stages_7_OtherBits_FA|N_5_i COUT } "NODE_NAME" } "" } } { "synplify_work/AdderE.vqm" "" { Text "E:/QProj/AdderEQ/synplify_work/AdderE.vqm" 399 46 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.195 ns 31.77 % " "Info: Total cell delay = 5.195 ns ( 31.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.156 ns 68.23 % " "Info: Total interconnect delay = 11.156 ns ( 68.23 % )" {  } {  } 0}  } { { "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" "" { Report "E:/QProj/AdderEQ/db/AdderE_cmp.qrpt" Compiler "AdderE" "UNKNOWN" "V1" "E:/QProj/AdderEQ/db/AdderE.quartus_db" { Floorplan "E:/QProj/AdderEQ/" "" "16.351 ns" { A[0] Full_Adder:Stages_0_LowBit_FA|COUT_x Full_Adder_2:Stages_1_OtherBits_FA|COUT_x_0 Full_Adder_5:Stages_2_OtherBits_FA|COUT_x_0 Full_Adder_6:Stages_3_OtherBits_FA|COUT_x_0 Full_Adder_7:Stages_4_OtherBits_FA|COUT_x_0 Full_Adder_4:Stages_5_OtherBits_FA|COUT_x_0 Full_Adder_1:Stages_6_OtherBits_FA|COUT_x_0 Full_Adder_3:Stages_7_OtherBits_FA|N_5_i COUT } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "16.351 ns" { A[0] A[0]~out0 Full_Adder:Stages_0_LowBit_FA|COUT_x Full_Adder_2:Stages_1_OtherBits_FA|COUT_x_0 Full_Adder_5:Stages_2_OtherBits_FA|COUT_x_0 Full_Adder_6:Stages_3_OtherBits_FA|COUT_x_0 Full_Adder_7:Stages_4_OtherBits_FA|COUT_x_0 Full_Adder_4:Stages_5_OtherBits_FA|COUT_x_0 Full_Adder_1:Stages_6_OtherBits_FA|COUT_x_0 Full_Adder_3:Stages_7_OtherBits_FA|N_5_i COUT } { 0.000ns 0.000ns 5.331ns 0.453ns 0.431ns 1.788ns 0.451ns 0.442ns 0.444ns 0.442ns 1.374ns } { 0.000ns 1.475ns 0.442ns 0.292ns 0.114ns 0.114ns 0.292ns 0.114ns 0.114ns 0.114ns 2.124ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri May 05 11:29:46 2006 " "Info: Processing ended: Fri May 05 11:29:46 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}