addere.vm

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

// @3:16
  cyclone_lcell COUT_x_1 (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.combout(COUT_x_0),
	.regout(),
	.cout(),
	.clk(),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_x),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.cin(GND),
	.inverta(GND),
	.aload(GND),
	.regcascin()
);
defparam COUT_x_1.operation_mode="normal";
defparam COUT_x_1.output_mode="comb_only";
defparam COUT_x_1.lut_mask="7171";
defparam COUT_x_1.synch_mode="off";
defparam COUT_x_1.sum_lutc_input="datac";
  assign GND = 1'b0;
  assign VCC = 1'b1;
endmodule /* Full_Adder_7 */

module AdderE (
  A,
  B,
  CIN,
  COUT,
  SUM
);
input [7:0] A ;
input [7:0] B ;
input CIN ;
output COUT /* synthesis syn_tristate = 1 */;
output [7:0] SUM /* synthesis syn_tristate = 1 */;
wire CIN ;
wire COUT ;
wire [7:0] B_c;
wire [7:0] A_c;
wire VCC ;
wire GND ;
wire CIN_c ;
wire \Stages.7.OtherBits.FA.SUM_x  ;
wire \Stages.6.OtherBits.FA.SUM_x  ;
wire \Stages.5.OtherBits.FA.SUM_x  ;
wire \Stages.4.OtherBits.FA.SUM_x  ;
wire \Stages.3.OtherBits.FA.SUM_x  ;
wire \Stages.2.OtherBits.FA.SUM_x  ;
wire \Stages.1.OtherBits.FA.SUM_x  ;
wire \Stages.0.LowBit.FA.SUM_x  ;
wire N_5_i ;
wire \Stages.0.LowBit.FA.COUT_x  ;
wire \Stages.6.OtherBits.FA.COUT_x  ;
wire \Stages.5.OtherBits.FA.COUT_x  ;
wire \Stages.1.OtherBits.FA.COUT_x  ;
wire \Stages.4.OtherBits.FA.COUT_x  ;
wire \Stages.2.OtherBits.FA.COUT_x  ;
wire \Stages.3.OtherBits.FA.COUT_x  ;
tri1 tridevclrn;
tri1 tridevpor;
tri0 tridevoe;
//@1:1
  assign VCC = 1'b1;
//@1:1
  assign GND = 1'b0;
// @2:5
  cyclone_io CIN_in (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(CIN),
	.regout(),
	.combout(CIN_c),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam CIN_in.operation_mode = "input";
// @2:4
  cyclone_io B_in_7_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(B[7]),
	.regout(),
	.combout(B_c[7]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam B_in_7_.operation_mode = "input";
// @2:4
  cyclone_io B_in_6_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(B[6]),
	.regout(),
	.combout(B_c[6]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam B_in_6_.operation_mode = "input";
// @2:4
  cyclone_io B_in_5_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(B[5]),
	.regout(),
	.combout(B_c[5]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam B_in_5_.operation_mode = "input";
// @2:4
  cyclone_io B_in_4_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(B[4]),
	.regout(),
	.combout(B_c[4]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam B_in_4_.operation_mode = "input";
// @2:4
  cyclone_io B_in_3_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(B[3]),
	.regout(),
	.combout(B_c[3]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam B_in_3_.operation_mode = "input";
// @2:4
  cyclone_io B_in_2_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(B[2]),
	.regout(),
	.combout(B_c[2]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam B_in_2_.operation_mode = "input";
// @2:4
  cyclone_io B_in_1_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(B[1]),
	.regout(),
	.combout(B_c[1]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam B_in_1_.operation_mode = "input";
// @2:4
  cyclone_io B_in_0_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(B[0]),
	.regout(),
	.combout(B_c[0]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam B_in_0_.operation_mode = "input";
// @2:4
  cyclone_io A_in_7_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(A[7]),
	.regout(),
	.combout(A_c[7]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam A_in_7_.operation_mode = "input";
// @2:4
  cyclone_io A_in_6_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(A[6]),
	.regout(),
	.combout(A_c[6]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam A_in_6_.operation_mode = "input";
// @2:4
  cyclone_io A_in_5_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(A[5]),
	.regout(),
	.combout(A_c[5]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam A_in_5_.operation_mode = "input";
// @2:4
  cyclone_io A_in_4_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(A[4]),
	.regout(),
	.combout(A_c[4]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam A_in_4_.operation_mode = "input";
// @2:4
  cyclone_io A_in_3_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(A[3]),
	.regout(),
	.combout(A_c[3]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam A_in_3_.operation_mode = "input";
// @2:4
  cyclone_io A_in_2_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(A[2]),
	.regout(),
	.combout(A_c[2]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam A_in_2_.operation_mode = "input";
// @2:4
  cyclone_io A_in_1_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(A[1]),
	.regout(),
	.combout(A_c[1]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam A_in_1_.operation_mode = "input";
// @2:4
  cyclone_io A_in_0_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(A[0]),
	.regout(),
	.combout(A_c[0]),
	.datain(),
	.oe(GND),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam A_in_0_.operation_mode = "input";
// @2:7
  cyclone_io SUM_out_7_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(SUM[7]),
	.regout(),
	.combout(),
	.datain(\Stages.7.OtherBits.FA.SUM_x ),
	.oe(VCC),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam SUM_out_7_.operation_mode = "output";
// @2:7
  cyclone_io SUM_out_6_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(SUM[6]),
	.regout(),
	.combout(),
	.datain(\Stages.6.OtherBits.FA.SUM_x ),
	.oe(VCC),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam SUM_out_6_.operation_mode = "output";
// @2:7
  cyclone_io SUM_out_5_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(SUM[5]),
	.regout(),
	.combout(),
	.datain(\Stages.5.OtherBits.FA.SUM_x ),
	.oe(VCC),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam SUM_out_5_.operation_mode = "output";
// @2:7
  cyclone_io SUM_out_4_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(SUM[4]),
	.regout(),
	.combout(),
	.datain(\Stages.4.OtherBits.FA.SUM_x ),
	.oe(VCC),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam SUM_out_4_.operation_mode = "output";
// @2:7
  cyclone_io SUM_out_3_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(SUM[3]),
	.regout(),
	.combout(),
	.datain(\Stages.3.OtherBits.FA.SUM_x ),
	.oe(VCC),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam SUM_out_3_.operation_mode = "output";
// @2:7
  cyclone_io SUM_out_2_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(SUM[2]),
	.regout(),
	.combout(),
	.datain(\Stages.2.OtherBits.FA.SUM_x ),
	.oe(VCC),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam SUM_out_2_.operation_mode = "output";
// @2:7
  cyclone_io SUM_out_1_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(SUM[1]),
	.regout(),
	.combout(),
	.datain(\Stages.1.OtherBits.FA.SUM_x ),
	.oe(VCC),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam SUM_out_1_.operation_mode = "output";
// @2:7
  cyclone_io SUM_out_0_ (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(SUM[0]),
	.regout(),
	.combout(),
	.datain(\Stages.0.LowBit.FA.SUM_x ),
	.oe(VCC),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam SUM_out_0_.operation_mode = "output";
// @2:6
  cyclone_io COUT_out (
	.devpor(tridevpor),
	.devclrn(tridevclrn),
	.devoe(tridevoe),
	.padio(COUT),
	.regout(),
	.combout(),
	.datain(N_5_i),
	.oe(VCC),
	.outclk(),
	.outclkena(VCC),
	.inclk(),
	.inclkena(VCC),
	.areset(GND),
	.sreset(GND)
);
defparam COUT_out.operation_mode = "output";
// @2:23
  Full_Adder Stages_0_LowBit_FA (
	.B_c_0(B_c[0]),
	.A_c_0(A_c[0]),
	.COUT_x(\Stages.0.LowBit.FA.COUT_x ),
	.CIN_c(CIN_c),
	.SUM_x(\Stages.0.LowBit.FA.SUM_x )
);
// @2:26
  Full_Adder_1 Stages_6_OtherBits_FA (
	.B_c_0(B_c[6]),
	.A_c_0(A_c[6]),
	.COUT_x_0(\Stages.6.OtherBits.FA.COUT_x ),
	.COUT_x(\Stages.5.OtherBits.FA.COUT_x ),
	.SUM_x(\Stages.6.OtherBits.FA.SUM_x )
);
// @2:26
  Full_Adder_2 Stages_1_OtherBits_FA (
	.B_c_0(B_c[1]),
	.A_c_0(A_c[1]),
	.COUT_x_0(\Stages.1.OtherBits.FA.COUT_x ),
	.COUT_x(\Stages.0.LowBit.FA.COUT_x ),
	.SUM_x(\Stages.1.OtherBits.FA.SUM_x )
);
// @2:26
  Full_Adder_3 Stages_7_OtherBits_FA (
	.B_c_0(B_c[7]),
	.A_c_0(A_c[7]),
	.N_5_i(N_5_i),
	.COUT_x(\Stages.6.OtherBits.FA.COUT_x ),
	.SUM_x(\Stages.7.OtherBits.FA.SUM_x )
);
// @2:26
  Full_Adder_4 Stages_5_OtherBits_FA (
	.B_c_0(B_c[5]),
	.A_c_0(A_c[5]),
	.COUT_x_0(\Stages.5.OtherBits.FA.COUT_x ),
	.COUT_x(\Stages.4.OtherBits.FA.COUT_x ),
	.SUM_x(\Stages.5.OtherBits.FA.SUM_x )
);
// @2:26
  Full_Adder_5 Stages_2_OtherBits_FA (
	.B_c_0(B_c[2]),
	.A_c_0(A_c[2]),
	.COUT_x_0(\Stages.2.OtherBits.FA.COUT_x ),
	.COUT_x(\Stages.1.OtherBits.FA.COUT_x ),
	.SUM_x(\Stages.2.OtherBits.FA.SUM_x )
);
// @2:26
  Full_Adder_6 Stages_3_OtherBits_FA (
	.B_c_0(B_c[3]),
	.A_c_0(A_c[3]),
	.COUT_x_0(\Stages.3.OtherBits.FA.COUT_x ),
	.COUT_x(\Stages.2.OtherBits.FA.COUT_x ),
	.SUM_x(\Stages.3.OtherBits.FA.SUM_x )
);
// @2:26
  Full_Adder_7 Stages_4_OtherBits_FA (
	.B_c_0(B_c[4]),
	.A_c_0(A_c[4]),
	.COUT_x_0(\Stages.4.OtherBits.FA.COUT_x ),
	.COUT_x(\Stages.3.OtherBits.FA.COUT_x ),
	.SUM_x(\Stages.4.OtherBits.FA.SUM_x )
);
endmodule /* AdderE */