addere.srr

来自「郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程」· SRR 代码 · 共 96 行

$ Start of Compile
#Fri May 05 11:29:31 2006

Synplicity VHDL Compiler, version Compilers 2.8.1, Build 050R, built Oct  6 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved

VHDL syntax check successful!

Compiler output is up to date.  No re-compile necessary

Synthesizing work.addere.syn
Synthesizing work.full_adder.syn
Post processing for work.full_adder.syn
Post processing for work.addere.syn
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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Synplicity Altera Technology Mapper, version 7.7.0, Build 054R, built Oct  6 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved
Reading constraint file: E:\QProj\AdderEQ\synplify_work\AdderE.sdc



Writing Analyst data base E:\QProj\AdderEQ\synplify_work\AdderE.srm
Writing Verilog Netlist and constraint files
Writing .vqm output for Quartus
Writing Cross reference file for Quartus to E:\QProj\AdderEQ\synplify_work\AdderE.xrf
Writing Verilog Simulation files


##### START OF TIMING REPORT #####[
# Timing Report written on Fri May 05 11:29:32 2006
#


Top view:               AdderE
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    E:\QProj\AdderEQ\synplify_work\AdderE.sdc
                       
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: NA






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]


##### START OF AREA REPORT #####[
Design view:work.AdderE(syn)
Selecting part EP1C6F256C8
@N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..

I/O ATOMs:       26

Total LUTs:  16 of 5980 ( 0%)
Logic resources:  16 ATOMs of 5980 ( 0%)
ATOM count by mode:
  normal:       16
  arithmetic:   0

ShiftTap:       0  (0 registers)
Total ESB:      0 bits   (0% of 81920)

ATOMs using regout pin: 0
  also using enable pin: 0
  also using combout pin: 0
ATOMs using combout pin: 16
Number of Inputs on ATOMs: 48
Number of Nets:   117

##### END OF AREA REPORT #####]

Mapper successful!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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