addere_alt.tcl

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

project -new
add_file -vhdl -lib work ../AdderE.vhd
add_file -vhdl -lib work ../Full_Adder.vhd
add_file -constraints AdderE.sdc
set_option -top_module AdderE
set_option -technology CYCLONE
set_option -part EP1C6
set_option -package FC256
set_option -speed_grade -8
set_option -write_verilog true
project -result_file ./AdderE.vqm
project -log_file ./AdderE.srr
project -run
project -save AdderE.prj