addere.xrf

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

vendor_name = Synplicity
source_file = 0, noname, synplify
source_file = 1, d:\synplicity\synplify_771\lib\vhd\std.vhd, synplify
source_file = 2, e:\qproj\addereq\addere.vhd, synplify
source_file = 3, e:\qproj\addereq\full_adder.vhd, synplify
design_name=AdderE
instance = port, A[7:0], , AdderE, 2, 4:3:4:3
instance = port, B[7:0], , AdderE, 2, 4:5:4:5
instance = port, CIN, , AdderE, 2, 5:3:5:5
instance = port, COUT, , AdderE, 2, 6:3:6:6
instance = port, SUM[7:0], , AdderE, 2, 7:3:7:5
instance = comp, CIN_in, , AdderE, 2, 5:3:5:5
instance = comp, B_in_7_, , AdderE, 2, 4:5:4:5
instance = comp, B_in_6_, , AdderE, 2, 4:5:4:5
instance = comp, B_in_5_, , AdderE, 2, 4:5:4:5
instance = comp, B_in_4_, , AdderE, 2, 4:5:4:5
instance = comp, B_in_3_, , AdderE, 2, 4:5:4:5
instance = comp, B_in_2_, , AdderE, 2, 4:5:4:5
instance = comp, B_in_1_, , AdderE, 2, 4:5:4:5
instance = comp, B_in_0_, , AdderE, 2, 4:5:4:5
instance = comp, A_in_7_, , AdderE, 2, 4:3:4:3
instance = comp, A_in_6_, , AdderE, 2, 4:3:4:3
instance = comp, A_in_5_, , AdderE, 2, 4:3:4:3
instance = comp, A_in_4_, , AdderE, 2, 4:3:4:3
instance = comp, A_in_3_, , AdderE, 2, 4:3:4:3
instance = comp, A_in_2_, , AdderE, 2, 4:3:4:3
instance = comp, A_in_1_, , AdderE, 2, 4:3:4:3
instance = comp, A_in_0_, , AdderE, 2, 4:3:4:3
instance = comp, SUM_out_7_, , AdderE, 2, 7:3:7:5
instance = comp, SUM_out_6_, , AdderE, 2, 7:3:7:5
instance = comp, SUM_out_5_, , AdderE, 2, 7:3:7:5
instance = comp, SUM_out_4_, , AdderE, 2, 7:3:7:5
instance = comp, SUM_out_3_, , AdderE, 2, 7:3:7:5
instance = comp, SUM_out_2_, , AdderE, 2, 7:3:7:5
instance = comp, SUM_out_1_, , AdderE, 2, 7:3:7:5
instance = comp, SUM_out_0_, , AdderE, 2, 7:3:7:5
instance = comp, COUT_out, , AdderE, 2, 6:3:6:6
instance = comp, Stages_0_LowBit_FA, , AdderE, 2, 23:3:23:4
instance = comp, Stages_6_OtherBits_FA, , AdderE, 2, 26:3:26:4
instance = comp, Stages_1_OtherBits_FA, , AdderE, 2, 26:3:26:4
instance = comp, Stages_7_OtherBits_FA, , AdderE, 2, 26:3:26:4
instance = comp, Stages_5_OtherBits_FA, , AdderE, 2, 26:3:26:4
instance = comp, Stages_2_OtherBits_FA, , AdderE, 2, 26:3:26:4
instance = comp, Stages_3_OtherBits_FA, , AdderE, 2, 26:3:26:4
instance = comp, Stages_4_OtherBits_FA, , AdderE, 2, 26:3:26:4
design_name=Full_Adder_7
instance = comp, SUM_x_0, , Full_Adder_7, 3, 15:8:15:20
instance = comp, COUT_x_1, , Full_Adder_7, 3, 16:9:16:25
design_name=Full_Adder_6
instance = comp, SUM_x_0, , Full_Adder_6, 3, 15:8:15:20
instance = comp, COUT_x_1, , Full_Adder_6, 3, 16:9:16:25
design_name=Full_Adder_5
instance = comp, SUM_x_0, , Full_Adder_5, 3, 15:8:15:20
instance = comp, COUT_x_1, , Full_Adder_5, 3, 16:9:16:25
design_name=Full_Adder_4
instance = comp, SUM_x_0, , Full_Adder_4, 3, 15:8:15:20
instance = comp, COUT_x_1, , Full_Adder_4, 3, 16:9:16:25
design_name=Full_Adder_3
instance = comp, SUM_x_0, , Full_Adder_3, 3, 15:8:15:20
instance = comp, COUT_x_0, , Full_Adder_3, 3, 16:9:16:25
design_name=Full_Adder_2
instance = comp, SUM_x_0, , Full_Adder_2, 3, 15:8:15:20
instance = comp, COUT_x_1, , Full_Adder_2, 3, 16:9:16:25
design_name=Full_Adder_1
instance = comp, SUM_x_0, , Full_Adder_1, 3, 15:8:15:20
instance = comp, COUT_x_1, , Full_Adder_1, 3, 16:9:16:25
design_name=Full_Adder
instance = comp, SUM_x_0, , Full_Adder, 3, 15:8:15:20
instance = comp, COUT_x_0, , Full_Adder, 3, 16:9:16:25