addere.srs

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

#
#
#
# Created by Synplify VHDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Sun Mar 26 12:20:54 2006
#
#
#OPTIONS:"|-top|AdderE|-fixsmult|-nram|-divnmod|-sm|-fid2|-sharing|off|-encrypt|-dfltencoding|onehot|-ui|-lite|-pro|-ram|-ignore_undefined_lib|-ll|2000|-lib|work|-lib|work"
#CUR:"D:\\Synplicity\\fpga_81\\bin\\c_vhdl.exe":1115125640
#CUR:"D:\\Synplicity\\fpga_81\\lib\\vhd\\location.map":1114701536
#CUR:"D:\\Synplicity\\fpga_81\\lib\\vhd\\std.vhd":1111509844
#CUR:"D:\\Synplicity\\fpga_81\\lib\\vhd\\std.vhd":1111509844
#CUR:"E:\\QProj\\AdderE syn\\Full_Adder.vhd":1140003728
#CUR:"E:\\QProj\\AdderE syn\\Full_Adder.vhd":1140003728
#CUR:"E:\\QProj\\AdderE syn\\AdderE.vhd":1140003726
#CUR:"E:\\QProj\\AdderE syn\\AdderE.vhd":1140003726
f "D:\Synplicity\fpga_81\lib\vhd\std.vhd"; # file 0
af .is_vhdl 1;
f "E:\QProj\AdderE syn\Full_Adder.vhd"; # file 1
af .is_vhdl 1;
f "E:\QProj\AdderE syn\AdderE.vhd"; # file 2
af .is_vhdl 1;
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