addere.qsf

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		AdderE_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:27:11  MAY 04, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name VQM_FILE "E:/QProj/AdderE/rev_1/AdderE.vqm"

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_G4 -to ~nCSO~
set_location_assignment PIN_K3 -to ~ASDO~
set_location_assignment PIN_A8 -to CIN
set_location_assignment PIN_C3 -to COUT
set_location_assignment PIN_B7 -to A[0]
set_location_assignment PIN_E8 -to A[1]
set_location_assignment PIN_C8 -to A[2]
set_location_assignment PIN_D6 -to A[3]
set_location_assignment PIN_D4 -to A[4]
set_location_assignment PIN_A4 -to A[5]
set_location_assignment PIN_H1 -to A[6]
set_location_assignment PIN_C2 -to A[7]
set_location_assignment PIN_B6 -to B[0]
set_location_assignment PIN_B8 -to B[1]
set_location_assignment PIN_C7 -to B[2]
set_location_assignment PIN_B2 -to B[3]
set_location_assignment PIN_B3 -to B[4]
set_location_assignment PIN_G1 -to B[5]
set_location_assignment PIN_C4 -to B[6]
set_location_assignment PIN_B5 -to B[7]
set_location_assignment PIN_A6 -to SUM[0]
set_location_assignment PIN_D7 -to SUM[1]
set_location_assignment PIN_D8 -to SUM[2]
set_location_assignment PIN_C5 -to SUM[3]
set_location_assignment PIN_E5 -to SUM[4]
set_location_assignment PIN_B1 -to SUM[5]
set_location_assignment PIN_A2 -to SUM[6]
set_location_assignment PIN_B4 -to SUM[7]

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL SYNPLIFY
set_global_assignment -name FAMILY CYCLONE
set_global_assignment -name TOP_LEVEL_ENTITY AdderE

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C6F256C8
set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON

# Timing Analysis Assignments
# ===========================
set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 1000
set_global_assignment -name TAO_FILE myresults.tao

# ---------------------------------------------
# start EDA_TOOL_SETTINGS(eda_design_synthesis)

	# Analysis & Synthesis Assignments
	# ================================
	set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis

# end EDA_TOOL_SETTINGS(eda_design_synthesis)
# -------------------------------------------