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📄 addere.vqm

📁 郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程
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12 
//
// Written by Synplify
// Synplify 8.1.0, Build 539R.
// Sun Mar 26 12:20:57 2006
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\synplicity\fpga_81\lib\vhd\std.vhd "
// file 2 "\e:\qproj\addere syn\full_adder.vhd "
// file 3 "\e:\qproj\addere syn\addere.vhd "

// VQM4.1+ 
module Full_Adder_Stages_0_LowBit_FA (
  B_c_0,
  A_c_0,
  COUT_x,
  CIN_c,
  SUM_x
);
input B_c_0 ;
input A_c_0 ;
output COUT_x ;
input CIN_c ;
output SUM_x ;
wire B_c_0 ;
wire A_c_0 ;
wire COUT_x ;
wire CIN_c ;
wire SUM_x ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:15
  cyclone_lcell SUM_x_cZ (
	.combout(SUM_x),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(CIN_c),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam SUM_x_cZ.operation_mode="normal";
defparam SUM_x_cZ.output_mode="comb_only";
defparam SUM_x_cZ.lut_mask="9696";
defparam SUM_x_cZ.synch_mode="off";
defparam SUM_x_cZ.sum_lutc_input="datac";
// @2:16
  cyclone_lcell COUT_x_cZ (
	.combout(COUT_x),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(CIN_c),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam COUT_x_cZ.operation_mode="normal";
defparam COUT_x_cZ.output_mode="comb_only";
defparam COUT_x_cZ.lut_mask="e8e8";
defparam COUT_x_cZ.synch_mode="off";
defparam COUT_x_cZ.sum_lutc_input="datac";
endmodule /* Full_Adder_Stages_0_LowBit_FA */

// VQM4.1+ 
module Full_Adder_Stages_0_LowBit_FA_1 (
  B_c_0,
  A_c_0,
  COUT_x_0,
  COUT_x,
  SUM_x
);
input B_c_0 ;
input A_c_0 ;
output COUT_x_0 ;
input COUT_x ;
output SUM_x ;
wire B_c_0 ;
wire A_c_0 ;
wire COUT_x_0 ;
wire COUT_x ;
wire SUM_x ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:15
  cyclone_lcell SUM_x_cZ (
	.combout(SUM_x),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_x),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam SUM_x_cZ.operation_mode="normal";
defparam SUM_x_cZ.output_mode="comb_only";
defparam SUM_x_cZ.lut_mask="9696";
defparam SUM_x_cZ.synch_mode="off";
defparam SUM_x_cZ.sum_lutc_input="datac";
// @2:16
  cyclone_lcell COUT_x_cZ (
	.combout(COUT_x_0),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_x),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam COUT_x_cZ.operation_mode="normal";
defparam COUT_x_cZ.output_mode="comb_only";
defparam COUT_x_cZ.lut_mask="e8e8";
defparam COUT_x_cZ.synch_mode="off";
defparam COUT_x_cZ.sum_lutc_input="datac";
endmodule /* Full_Adder_Stages_0_LowBit_FA_1 */

// VQM4.1+ 
module Full_Adder_Stages_0_LowBit_FA_2 (
  B_c_0,
  A_c_0,
  COUT_x_0,
  COUT_x,
  SUM_x
);
input B_c_0 ;
input A_c_0 ;
output COUT_x_0 ;
input COUT_x ;
output SUM_x ;
wire B_c_0 ;
wire A_c_0 ;
wire COUT_x_0 ;
wire COUT_x ;
wire SUM_x ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:15
  cyclone_lcell SUM_x_cZ (
	.combout(SUM_x),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_x),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam SUM_x_cZ.operation_mode="normal";
defparam SUM_x_cZ.output_mode="comb_only";
defparam SUM_x_cZ.lut_mask="9696";
defparam SUM_x_cZ.synch_mode="off";
defparam SUM_x_cZ.sum_lutc_input="datac";
// @2:16
  cyclone_lcell COUT_x_cZ (
	.combout(COUT_x_0),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_x),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam COUT_x_cZ.operation_mode="normal";
defparam COUT_x_cZ.output_mode="comb_only";
defparam COUT_x_cZ.lut_mask="e8e8";
defparam COUT_x_cZ.synch_mode="off";
defparam COUT_x_cZ.sum_lutc_input="datac";
endmodule /* Full_Adder_Stages_0_LowBit_FA_2 */

// VQM4.1+ 
module Full_Adder_Stages_0_LowBit_FA_3 (
  B_c_0,
  A_c_0,
  COUT_x_0,
  COUT_x,
  SUM_x
);
input B_c_0 ;
input A_c_0 ;
output COUT_x_0 ;
input COUT_x ;
output SUM_x ;
wire B_c_0 ;
wire A_c_0 ;
wire COUT_x_0 ;
wire COUT_x ;
wire SUM_x ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:15
  cyclone_lcell SUM_x_cZ (
	.combout(SUM_x),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_x),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam SUM_x_cZ.operation_mode="normal";
defparam SUM_x_cZ.output_mode="comb_only";
defparam SUM_x_cZ.lut_mask="9696";
defparam SUM_x_cZ.synch_mode="off";
defparam SUM_x_cZ.sum_lutc_input="datac";
// @2:16
  cyclone_lcell COUT_x_cZ (
	.combout(COUT_x_0),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_x),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam COUT_x_cZ.operation_mode="normal";
defparam COUT_x_cZ.output_mode="comb_only";
defparam COUT_x_cZ.lut_mask="e8e8";
defparam COUT_x_cZ.synch_mode="off";
defparam COUT_x_cZ.sum_lutc_input="datac";
endmodule /* Full_Adder_Stages_0_LowBit_FA_3 */

// VQM4.1+ 
module Full_Adder_Stages_0_LowBit_FA_4 (
  B_c_0,
  A_c_0,
  COUT_x_0,
  COUT_x,
  SUM_x
);
input B_c_0 ;
input A_c_0 ;
output COUT_x_0 ;
input COUT_x ;
output SUM_x ;
wire B_c_0 ;
wire A_c_0 ;
wire COUT_x_0 ;
wire COUT_x ;
wire SUM_x ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:15
  cyclone_lcell SUM_x_cZ (
	.combout(SUM_x),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_x),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam SUM_x_cZ.operation_mode="normal";
defparam SUM_x_cZ.output_mode="comb_only";
defparam SUM_x_cZ.lut_mask="9696";
defparam SUM_x_cZ.synch_mode="off";
defparam SUM_x_cZ.sum_lutc_input="datac";
// @2:16
  cyclone_lcell COUT_x_cZ (
	.combout(COUT_x_0),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_x),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam COUT_x_cZ.operation_mode="normal";
defparam COUT_x_cZ.output_mode="comb_only";
defparam COUT_x_cZ.lut_mask="e8e8";
defparam COUT_x_cZ.synch_mode="off";
defparam COUT_x_cZ.sum_lutc_input="datac";
endmodule /* Full_Adder_Stages_0_LowBit_FA_4 */

// VQM4.1+ 
module Full_Adder_Stages_0_LowBit_FA_5 (
  B_c_0,
  A_c_0,
  COUT_x_0,
  COUT_x,
  SUM_x
);
input B_c_0 ;
input A_c_0 ;
output COUT_x_0 ;
input COUT_x ;
output SUM_x ;
wire B_c_0 ;
wire A_c_0 ;
wire COUT_x_0 ;
wire COUT_x ;
wire SUM_x ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:15
  cyclone_lcell SUM_x_cZ (
	.combout(SUM_x),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_x),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam SUM_x_cZ.operation_mode="normal";
defparam SUM_x_cZ.output_mode="comb_only";
defparam SUM_x_cZ.lut_mask="9696";
defparam SUM_x_cZ.synch_mode="off";
defparam SUM_x_cZ.sum_lutc_input="datac";
// @2:16
  cyclone_lcell COUT_x_cZ (
	.combout(COUT_x_0),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_x),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam COUT_x_cZ.operation_mode="normal";
defparam COUT_x_cZ.output_mode="comb_only";
defparam COUT_x_cZ.lut_mask="e8e8";
defparam COUT_x_cZ.synch_mode="off";
defparam COUT_x_cZ.sum_lutc_input="datac";
endmodule /* Full_Adder_Stages_0_LowBit_FA_5 */

// VQM4.1+ 
module Full_Adder_Stages_0_LowBit_FA_6 (
  B_c_0,
  A_c_0,
  COUT_x_0,
  COUT_x,
  SUM_x
);
input B_c_0 ;
input A_c_0 ;
output COUT_x_0 ;
input COUT_x ;
output SUM_x ;
wire B_c_0 ;
wire A_c_0 ;
wire COUT_x_0 ;
wire COUT_x ;
wire SUM_x ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:15
  cyclone_lcell SUM_x_cZ (
	.combout(SUM_x),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_x),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam SUM_x_cZ.operation_mode="normal";
defparam SUM_x_cZ.output_mode="comb_only";
defparam SUM_x_cZ.lut_mask="9696";
defparam SUM_x_cZ.synch_mode="off";
defparam SUM_x_cZ.sum_lutc_input="datac";
// @2:16
  cyclone_lcell COUT_x_cZ (
	.combout(COUT_x_0),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_x),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
	.inverta(GND),
	.aload(GND),
	.regcascin(GND)
);
defparam COUT_x_cZ.operation_mode="normal";
defparam COUT_x_cZ.output_mode="comb_only";
defparam COUT_x_cZ.lut_mask="e8e8";
defparam COUT_x_cZ.synch_mode="off";
defparam COUT_x_cZ.sum_lutc_input="datac";
endmodule /* Full_Adder_Stages_0_LowBit_FA_6 */

// VQM4.1+ 
module Full_Adder_Stages_0_LowBit_FA_7 (
  B_c_0,
  A_c_0,
  COUT_x_0,
  COUT_x,
  SUM_x
);
input B_c_0 ;
input A_c_0 ;
output COUT_x_0 ;
input COUT_x ;
output SUM_x ;
wire B_c_0 ;
wire A_c_0 ;
wire COUT_x_0 ;
wire COUT_x ;
wire SUM_x ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:15
  cyclone_lcell SUM_x_cZ (
	.combout(SUM_x),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_x),
	.datad(VCC),
	.aclr(GND),
	.sclr(GND),
	.sload(GND),
	.ena(VCC),
12

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