addere.map.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 04 16:42:26 2006 " "Info: Processing started: Thu May 04 16:42:26 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AdderE -c AdderE " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off AdderE -c AdderE" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AdderE.vqm 9 9 " "Info: Found 9 design units, including 9 entities, in source file AdderE.vqm" { { "Info" "ISGN_ENTITY_NAME" "1 Full_Adder " "Info: Found entity 1: Full_Adder" {  } { { "AdderE.vqm" "" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 13 18 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 Full_Adder_1 " "Info: Found entity 2: Full_Adder_1" {  } { { "AdderE.vqm" "" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 60 20 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 Full_Adder_2 " "Info: Found entity 3: Full_Adder_2" {  } { { "AdderE.vqm" "" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 107 20 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 Full_Adder_3 " "Info: Found entity 4: Full_Adder_3" {  } { { "AdderE.vqm" "" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 154 20 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "5 Full_Adder_4 " "Info: Found entity 5: Full_Adder_4" {  } { { "AdderE.vqm" "" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 201 20 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "6 Full_Adder_5 " "Info: Found entity 6: Full_Adder_5" {  } { { "AdderE.vqm" "" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 248 20 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "7 Full_Adder_6 " "Info: Found entity 7: Full_Adder_6" {  } { { "AdderE.vqm" "" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 295 20 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "8 Full_Adder_7 " "Info: Found entity 8: Full_Adder_7" {  } { { "AdderE.vqm" "" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 342 20 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "9 AdderE " "Info: Found entity 9: AdderE" {  } { { "AdderE.vqm" "" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 389 14 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "AdderE " "Info: Elaborating entity \"AdderE\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Full_Adder Full_Adder:Stages_0_LowBit_FA " "Info: Elaborating entity \"Full_Adder\" for hierarchy \"Full_Adder:Stages_0_LowBit_FA\"" {  } { { "AdderE.vqm" "Stages_0_LowBit_FA" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 617 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Full_Adder_1 Full_Adder_1:Stages_6_OtherBits_FA " "Info: Elaborating entity \"Full_Adder_1\" for hierarchy \"Full_Adder_1:Stages_6_OtherBits_FA\"" {  } { { "AdderE.vqm" "Stages_6_OtherBits_FA" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 625 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Full_Adder_2 Full_Adder_2:Stages_1_OtherBits_FA " "Info: Elaborating entity \"Full_Adder_2\" for hierarchy \"Full_Adder_2:Stages_1_OtherBits_FA\"" {  } { { "AdderE.vqm" "Stages_1_OtherBits_FA" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 633 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Full_Adder_3 Full_Adder_3:Stages_7_OtherBits_FA " "Info: Elaborating entity \"Full_Adder_3\" for hierarchy \"Full_Adder_3:Stages_7_OtherBits_FA\"" {  } { { "AdderE.vqm" "Stages_7_OtherBits_FA" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 641 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Full_Adder_4 Full_Adder_4:Stages_5_OtherBits_FA " "Info: Elaborating entity \"Full_Adder_4\" for hierarchy \"Full_Adder_4:Stages_5_OtherBits_FA\"" {  } { { "AdderE.vqm" "Stages_5_OtherBits_FA" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 649 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Full_Adder_5 Full_Adder_5:Stages_2_OtherBits_FA " "Info: Elaborating entity \"Full_Adder_5\" for hierarchy \"Full_Adder_5:Stages_2_OtherBits_FA\"" {  } { { "AdderE.vqm" "Stages_2_OtherBits_FA" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 657 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Full_Adder_6 Full_Adder_6:Stages_3_OtherBits_FA " "Info: Elaborating entity \"Full_Adder_6\" for hierarchy \"Full_Adder_6:Stages_3_OtherBits_FA\"" {  } { { "AdderE.vqm" "Stages_3_OtherBits_FA" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 665 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Full_Adder_7 Full_Adder_7:Stages_4_OtherBits_FA " "Info: Elaborating entity \"Full_Adder_7\" for hierarchy \"Full_Adder_7:Stages_4_OtherBits_FA\"" {  } { { "AdderE.vqm" "Stages_4_OtherBits_FA" { Text "E:/QProj/AdderE/rev_1/AdderE.vqm" 673 3 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "42 " "Info: Implemented 42 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "17 " "Info: Implemented 17 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "16 " "Info: Implemented 16 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 04 16:42:32 2006 " "Info: Processing ended: Thu May 04 16:42:32 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}